ASIC RTL Design Lead

Mulya Technologies; Bengaluru; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks a Senior ASIC Engineer focused on IP RTL design targeted for SOC and static checks. You will contribute to RTL quality checks, timing concepts and AMBA protocol understanding while collaborating with design and verification teams.

Experience with IP design, subsystem integration and scripting is beneficial; familiarity with ARM debug architecture is a plus. The role involves multi-subsystem support and review of design docs.

Qualifications

• Expertise in IP design, subsystem/cluster and SoC level integration using Verilog/SystemVerilog.
• In-depth knowledge of RTL quality checks (Lint, CDC) and timing concepts.
• Familiarity with AMBA bus protocols (AXI, AHB, ATB, APB) and basic protocols.

Responsibilities

• Design, review and integrate IP RTL blocks for SOC subsystems.
• Support RTL quality checks and timing closure across subsystems.
• Collaborate with PD, verification, DFT and SW teams on design reviews.

Skills

RTL Design

RTL Coding

RTL Integration

RTL quality checks

IP design

SOC target

Static checks

AMBA protocols

DDR

I2C UART SPI

Tools

Spyglass Lint/CDC

Synopsys DC

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)

Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)

Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

In depth knowledge on RTL quality checks (Lint, CDC)

Knowledge of synthesis and low power is a plus

Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

Good understanding of timing concepts

Knowledge of one or more of the interface protocols

• b. DDR
• c. Ethernet
• d. I2C, UART, SPI

Expertise in setting up and using tools like

• a. Spyglass Lint/CDC
• b. Synopsys DC

Understanding of scripting languages like Make flow, Perl ,shell, python etc

Understanding of processor architecture and/or ARM debug architecture is a plus

Able to help and debug issues for multiple subsystems

Able to create/review design documents for multiple subsystems

Able to support physical design, verification, DFT and SW teams on design queries and reviews