Static Timing Analysis STA Engineer

Weekday AI (YC W21); Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Weekday AI (YC W21) is seeking an experienced STA Engineer to drive pre-layout and post-layout timing analysis for Bengaluru-based designs, ensuring timing closure across block-level and full-chip implementations.

The ideal candidate will master timing signoff, SDC constraints, MCMM, and clock analysis, with hands-on PrimeTime and Tcl scripting experience, contributing to signoff-ready tapeouts within a collaborative, global team.

Qualifications

• Extensive experience in Static Timing Analysis (STA) for block-level and full-chip designs.
• Strong expertise in timing signoff, SDC constraints, and clock analysis.

Responsibilities

• Perform pre-layout and post-layout STA for block-level and full-chip designs.
• Drive timing analysis and signoff across multiple design stages through tapeout.
• Develop, review, and optimize SDC timing constraints.
• Perform MCMM timing analysis and signoff.
• Address setup and hold timing violations to achieve timing closure.
• Perform OCV, AOCV, and POCV analyses for signoff.
• Conduct detailed clock analysis including latency, skew, and uncertainty.
• Identify bottlenecks and coordinate with RTL, Physical Design, DFT, and other teams.
• Develop Tcl-based automation for STA analysis and reporting.
• Support full-chip timing signoff and readiness for tapeout.
• Collaborate with cross-functional teams across distributed sites.

Skills

STA

Timing signoff

SDC constraints

MCMM

OCV

AOCV

POCV

Tcl scripting

Clock analysis

RTL collaboration

Physical Design collaboration

DFT collaboration

Tools

PrimeTime

Job description

Job Description:

This role is for one of Weekday’s clients

Min Experience: 4+ years
Location: Bengaluru, Karnataka
JobType: full-time

We are looking for an experienced Static Timing Analysis (STA) Engineer to drive pre-layout and post-layout timing analysis and ensure timing closure across block-level and full-chip designs. The ideal candidate will have strong expertise in timing signoff, SDC constraints, MCMM analysis, variation methodologies, and clock analysis, with hands-on experience using Synopsys PrimeTime and Tcl.

Key Responsibilities

• Perform pre-layout and post-layout STA for block-level and full-chip designs.
• Drive timing analysis and signoff across multiple design stages through tapeout.
• Develop, review, and optimize SDC timing constraints.
• Perform MCMM (Multi-Corner Multi-Mode) timing analysis and signoff.
• Analyze and address setup and hold timing violations to achieve complete timing closure.
• Perform OCV, AOCV, and POCV analysis for accurate timing signoff.
• Conduct detailed clock analysis, including clock latency, skew, uncertainty, and timing interactions.
• Identify timing bottlenecks and work closely with RTL, Physical Design, DFT, and other engineering teams to resolve issues.
• Develop and maintain Tcl-based automation for STA analysis and reporting.
• Support full-chip timing signoff activities and ensure design readiness for tapeout.
• Collaborate with cross-functional and geographically distributed engineering teams throughout the implementation cycle.

Required Skills & Qualifications

• Strong hands-on experience in Static Timing Analysis (STA).
• Expertise in Synopsys PrimeTime.
• Strong knowledge of SDC constraints and timing methodologies.
• Experience with setup/hold analysis and timing closure.
• Hands-on experience with MCMM, OCV, AOCV, and POCV.
• Strong Tcl scripting skills.
• Understanding of clock analysis and timing signoff methodologies.
• Experience working with RTL, Physical Design, and DFT teams in advanced semiconductor design environments.

Must-Have Skills

• STA
• PrimeTime
• Timing Closure

Good-to-Have Skills

• Full-Chip STA
• SDC
• Tcl Scripting
• MCMM
• OCV/AOCV/POCV
• Clock Analysis & Signoff