Lead Static Timing Analysis Engineer (STA)

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd); Chennai District; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd) is seeking an experienced STA Lead to drive static timing analysis and timing closure for complex ASIC/SoC designs across Chennai and Malaysia. You will lead block-level and full-chip STA activities, develop SDC constraints, and mentor engineers across RTL, synthesis and physical design.

The role requires deep PrimeTime expertise, strong debugging and leadership skills, and hands-on work with timing sign-off across multiple corners.

Qualifications

• Hands-on experience with Synopsys PrimeTime for STA and timing closure.
• Expertise in STA, timing closure and SDC.
• Knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
• Experience with block- and full-chip timing sign-off.
• Strong understanding of ASIC design flow and physical design.
• Scripting skills in Tcl/Perl/Python.

Responsibilities

• Lead block-level and full-chip STA activities.
• Develop and review SDC constraints.
• Handle setup, hold, recovery and removal analysis.
• Perform MMMC timing analysis across multiple PVT corners.
• Work on OCV, AOCV, POCV, SI and crosstalk analysis.
• Debug critical timing paths and drive timing closure.
• Review false paths, multicycle paths and generated clock constraints.
• Work closely with RTL, synthesis and physical design teams.
• Support ECO generation and final timing sign-off.
• Mentor junior engineers and drive STA deliverables.

Skills

PrimeTime

STA & timing closure

SDC constraints

MMMC/OCV/AOCV/POCV

Timing sign-off

ASIC/SoC timing

Scripting: Tcl/Perl/Python

Debugging & leadership

Job description

We are looking for an experienced STA Lead with strong expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.

We are looking for an experienced STA Lead with strong expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.

About the Role

We are looking for an experienced STA Lead with strong expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.

Responsibilities

• Lead block-level and full-chip STA activities.
• Develop and review SDC constraints.
• Handle setup, hold, recovery and removal analysis.
• Perform MMMC timing analysis across multiple PVT corners.
• Work on OCV, AOCV, POCV, SI and crosstalk analysis.
• Debug critical timing paths and drive timing closure.
• Review false paths, multicycle paths and generated clock constraints.
• Work closely with RTL, synthesis and physical design teams.
• Support ECO generation and final timing sign-off.
• Mentor junior engineers and drive STA deliverables.

Qualifications

• Strong hands-on experience with Synopsys PrimeTime.
• Expertise in STA, timing closure and SDC.
• Good knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
• Experience with block and full-chip timing sign-off.
• Strong understanding of ASIC design flow and physical design.
• Good scripting skills in Tcl/Perl/Python.
• Strong debugging, communication and team leadership skills.

Required Skills

• Strong hands-on experience with Synopsys PrimeTime.
• Expertise in STA, timing closure and SDC.
• Good knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
• Experience with block and full-chip timing sign-off.
• Strong understanding of ASIC design flow and physical design.
• Good scripting skills in Tcl/Perl/Python.
• Strong debugging, communication and team leadership skills.

Preferred Skills

• Strong hands-on experience with Synopsys PrimeTime.
• Expertise in STA, timing closure and SDC.
• Good knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
• Experience with block and full-chip timing sign-off.
• Strong understanding of ASIC design flow and physical design.
• Good scripting skills in Tcl/Perl/Python.
• Strong debugging, communication and team leadership skills.

Location

• Chennai and Malaysia

Equal Opportunity Statement

We are committed to diversity and inclusivity.