STA Lead Engineer

Mulya Technologies; Ernakulam; On-site; INR 3,000,000 - 5,200,000; Full time

Job summary

Mulya Technologies in Kochi is seeking a Lead STA Engineer with 11+ years of experience to ensure timing closure for complex SoC designs. You will analyze, validate, and optimize timing across hierarchies to meet performance and reliability targets.

You will work with RTL, DFT, synthesis, and physical design teams, develop SDC constraints, and drive ECOs, while crafting automation scripts (Tcl, Python) to streamline STA flows.

Qualifications

• 11+ years of STA experience in SoC/ASIC design.
• Strong understanding of timing closure, constraints, and sign-off.
• Experience across multiple corners, modes, and technology nodes.
• Ability to mentor junior engineers.

Responsibilities

• Perform STA at block and full-chip levels across corners, modes, and conditions.
• Create and validate SDC constraints for hierarchical SoC designs.
• Drive timing closure during synthesis, place-and-route, and sign-off; generate timing ECOs.
• Collaborate with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues.
• Develop scripts (Tcl, Python, Perl) to automate STA flows and reporting.
• Handle OCV, noise, crosstalk, and derating methodologies for accurate timing sign-off.
• Document STA methodology and participate in design reviews.
• Mentor junior engineers on STA techniques.

Skills

Digital design basics

Clocking concepts

STA knowledge

Scripting (Tcl/Python)

OCV/derating

Collaboration

Tools

Synopsys PrimeTime

Cadence Tempus

SDC constraints

SoC design

Tcl/Python scripting

ECO generation

Job description

Lead STA Engineer

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Bangalore /Hyderabad/Kochi

Role Overview

As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing closure and sign-off for complex System-on-Chip/Subsystem designs. This involves analyzing, validating, and optimizing timing across multiple design hierarchies and technology nodes to meet performance, power, and reliability targets.

Key Responsibilities

• Static Timing Analysis (STA):
• Perform STA at block and full-chip levels across multiple corners, modes, and conditions using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).
• Timing Constraints Development:
• Create and validate SDC constraints for hierarchical SoC designs, including clocking, multi-mode, and multi-corner scenarios.
• Timing Closure:
• Drive timing closure during synthesis, place-and-route, and sign-off stages. Generate timing ECOs and collaborate with physical design teams for optimization.
• Cross-Functional Collaboration:
• Work closely with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues and ensure design quality.
• Automation & Scripting:
• Develop scripts (Tcl, Python, Perl) to automate STA flows, reporting, and constraint validation.
• Advanced Analysis:
• Handle OCV (On-Chip Variation), noise, crosstalk, and derate methodologies for accurate timing sign-off.
• Documentation & Reviews:
• Maintain STA methodology documents and participate in design reviews.
• Mentorship:
• Guide junior engineers on STA techniques and best practices.

Required Skills & Tools

• Strong understanding of digital design principles, clocking, and timing concepts.
• Skills:
• Tempus
• Primetime
• SoC
• SDC
• MMMC
• ECO
• OCV