Static Timing Analysis Engineer

Accenture in India; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Accenture in India in Bengaluru is seeking a Static Timing Analysis Engineer with 7.5+ years of experience to analyze and verify timing of digital circuits. You will identify critical timing paths, optimize timing, and resolve setup/hold violations.

Collaborate with design and verification teams to refine timing models and improve circuit performance across clock speeds. This role requires attention to detail, SME-level expertise, and the ability to mentor junior team members while driving best

Qualifications

• Must have proficiency in Static Timing Analysis.
• Strong understanding of digital circuit design principles.
• Experience with timing analysis tools and methodologies.
• Ability to analyze complex timing issues and provide effective solutions.
• Familiarity with design verification processes and tools.

Responsibilities

• Full Chip level Constraints development, validation, and timing closure.
• Deep understanding of Finfet low technology node 7nm and below.
• Expertise on IO budgeting, MMMC timing eco generation and convergence.
• Expertise in Clock Tree analysis for deep submicron.
• Hands-on experience with industry standard tools like PrimeTime, Tempus, Fishtail etc.
• Deep understanding of AOCV, POCV margin methodology.
• Experience in Hyperscale, ILM is advantage.
• Collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Mentor junior team members to enhance their skills and knowledge in timing analysis.
• Continuously evaluate and implement best practices in static timing analysis to improve team performance.

Skills

Static Timing Analysis

Digital circuit design

Timing tools

Mentoring

Education

15 years of full-time education

Tools

PrimeTime

Tempus

Fishtail

Job description

Project Role : Static Timing Analysis Engineer

Project Role Description : Analyze and verify the timing of digital circuits to ensure they meet performance requirements under various operating conditions. Identify critical timing paths, perform timing optimizations, and resolve setup/hold violations to ensure the design functions correctly at the desired clock speeds. Collaborate with design and verification teams to refine timing models and improve circuit performance.

Must have skills : Static Timing Analysis (STA)

Good to have skills : NA

Minimum 7.5 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary: As a Static Timing Analysis Engineer, you will analyze and verify the timing of digital circuits to ensure they meet performance requirements under various operating conditions. Your typical day will involve identifying critical timing paths, performing timing optimizations, and resolving setup and hold violations. You will collaborate with design and verification teams to refine timing models and improve circuit performance, ensuring that the design functions correctly at the desired clock speeds. This role requires a keen attention to detail and a proactive approach to problem-solving, as you will be instrumental in enhancing the overall efficiency and reliability of digital designs.

Roles & Responsibilities:

• Full Chip level Constraints development, validation, and timing closure
• Deep understanding of Finfet low technology node 7nm and below
• Expertise on IO budgeting, MMMC timing eco generation and convergence
• Expertise in Clock Tree analysis for deep submicron
• Hands-on experience with industry standard tools like PrimeTime, Tempus, Fishtail etc
• Deep understanding of AOCV, POCV margin methodology
• Experience in Hyperscale, ILM is advantage
• Expected to be an SME.
• Collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Mentor junior team members to enhance their skills and knowledge in timing analysis.
• Continuously evaluate and implement best practices in static timing analysis to improve team performance.

Professional & Technical Skills:

• Must To Have Skills: Proficiency in Static Timing Analysis.
• Strong understanding of digital circuit design principles.
• Experience with timing analysis tools and methodologies.
• Ability to analyze complex timing issues and provide effective solutions.
• Familiarity with design verification processes and tools.

Additional Information:

• The candidate should have minimum 7.5 years of experience in Static Timing Analysis.
• This position is based at our Bengaluru office.
• A 15 years full time education is required.