Lead Static Timing Analysis (STA) Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an experienced Static Timing Analysis (STA) Engineer to own timing sign-off for complex ICs/SoCs. You will define constraints, perform MMMC analysis, and collaborate with design and physical design teams to meet target frequency and performance goals.

The role requires 6–10 years of STA experience, strong scripting skills, and hands-on expertise with EDA tools such as Fusion Compiler, ICC2, Primetime, Innovus, and Mentor Graphics.

Qualifications

• 6–10 years of hands-on STA experience required.
• Expertise in SDC constraints and MMMC timing.
• Strong scripting and automation skills.

Responsibilities

• Own timing sign-off for blocks, sub-systems, or full chip.
• Drive timing closure from pre-layout to post-layout.
• Develop, validate, and maintain SDC and timing constraints across modes.
• Perform MMMC timing across PVT corners and modes.
• Identify and debug critical paths to resolve Setup/Hold violations.
• Incorporate OCV, crosstalk, and IR-drop aware SA into sign-off.

Skills

Timing Analysis

EDA Scripting

Cross-functional collaboration

Education

Bachelor's or Master's in EE/Electronics/VLSI

Tools

Fusion Compiler

ICC2

Primetime

Innovus

Mentor Graphics

Job description

Lead Static Timing Analysis (STA) Engineer

Experience: 6 to 10 years of experience in STA.

Job Summary

The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.

Key Responsibilities

• Timing Sign-off and Analysis
• Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.
• Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).
• MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).
• Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations.
• Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.

Methodology and Flow

• Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.
• Automate repetitive tasks and report generation using scripting languages.
• Generate final timing reports and sign-off collateral for tape-out.

Education

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills

• EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.