Staff Engineer

Broadcom; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Broadcom Central Engineering is seeking a Multi-Skilled RTL, Verification engineer with DFT expertise to work across RTL, Verification and DFT domains for complex memory and IO subsystems. The role includes building verification suites, ensuring sign-off, and contributing to end-to-end chip development flow with emphasis on RTL, Synthesis and Memory BIST.

Candidate will verify complex digital subsystems using OVM/UVM, LEC, and Spyglass techniques, while collaborating with cross-functional teams

Qualifications

• RTL development and verification for Digital subsystems
• Memory Subsystems with MBIST and Tessent/Embedded MBIST
• DFT flows including MBIST, ATPG, RSQ and verification sign-off
• Formal verification, Cross Clock Domain checks, Power/Timing sign-off
• Verification using OVM/UVM methodologies and building verification environments

Responsibilities

• RTL development and Verification for Digital subsystems, Memory Subsystems including BIST.
• Memory Digital Subsystems with Tessent/Embedded MBIST
• MBIST, ATPG, RSQ Verification and sign-off.
• Formal verification, Cross Clock Domain checks, Power/Timing sign off
• Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suite Independently.

Skills

RTL

Synthesis

DFT

Verification methodologies

OVM/UVM

Formal verification

Cross Clock Domain checks

Power/Timing sign-off

Verilog

Tools

Spyglass

LEC

CDC

DC Ultra

Fusion Compiler

GLS

Verilog NC

Verilog XL

Job description

Job Description

Broadcom Central Engineering team is looking for a Multi Skilled RTL, Verification engineer with DFT expertise. The Successful candidate will work in one or more domains of RTL, Verification, DFT for Complex Memory, IO subsystems, Hierarchical Blocks including BIST. It is a great opportunity and challenging role for the people who want to gain in-depth knowledge on end to end chip development flow with deeper expertise on RTL, Synth and Memory BIST

Responsibilities

• RTL development and Verification for Digital subsystems, Memory Subsystems including BIST.
• Memory Digital Subsystems with Tessent/Embedded MBIST
• MBIST, ATPG, RSQ Verification and sign-off.
• Formal verification, Cross Clock Domain checks, Power/Timing sign off
• Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently.

Requirements

• Hands on Experience with RTL, Synthesis,
• Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs
• Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the DFT signoff.
• Familiarity with Spyglass, LEC, CDC, and Synthesis tools DC Ultra, Fusion Compiler.
• Familiarity with GLS, simulation, UVM, OVM methodologies is a big plus
• Proficiency with Verilog NC, Verilog XL tools
• Strong fundamentals in digital design and Coding/Verifying complex RTL subsystems

R027147