Design Engineer RTL

Digital Core Technologies Pvt Ltd; Ernakulam; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Digital Core Technologies Pvt Ltd in Kerala seeks an experienced RTL/FPGA engineer to design, verify, and optimize HDL-based digital IP. You will work with Verilog/VHDL/SystemVerilog, AMBA/AXI, and high-speed interfaces to ensure clean synthesis and efficient resource usage.

Ideal candidates have 3+ years of RTL/FPGA experience, familiarity with Xilinx/Intel toolchains, scripting (Python/Tcl), and hands-on lab debugging. Collaboration across teams is essential in this role.

Qualifications

• HDL and RTL expertise required for clean, synthesizable designs.
• Strong foundation in RTL, microarchitecture, AMBA/AXI, and FSMs.
• Analytical and mathematical problem-solving abilities.
• Solid knowledge of timing paths, CDC and STA.
• RTL simulation and verification experience.
• Familiarity with FPGA/SoC architectures and development tools.
• Exposure to AMD Zynq SoCs, ARM processing and AMBA/AXI.
• Ability to optimize speed, power, and area and integrate IP cores.
• Experience with I2C, SPI, UART interfaces; high-speed interfaces like MIPI, DDR, PCIe, USB, Ethernet, LVDS.
• Scripting for automation (Tcl, Python) and Git version control.
• Lab testing with logic analyzers and on-chip debugging.
• Basic reading of circuit schematics; digital and analog electronics knowledge.
• Desired: basic digital image/video processing or hardware DSP pipelines.
• Programming in Python, Matlab, C++ for software simulation before RTL implementation.

Skills

HDLs

RTL design fundamentals

AMBA/AXI

Pipelining

FSMs

Digital design

Analytical skills

Mathematics

Timing analysis

CDC

STA

RTL simulation

Verification

FPGA architectures

Development tools

Zynq

ARM processing

RTL optimization

IP cores

I2C

SPI

UART

MIPI CSI/DSI

DDR

PCIe

USB

Ethernet

LVDS

Tcl

Python

Git

Lab testing

Circuit schematics

Digital image processing

Hardware DSP pipelines

Job description

• Excellent skill in HDLs (Verilog, VHDL, and System Verilog) for writing clean, synthesizable RTL.
• Solid understanding of RTL design fundamentals, microarchitecture, AMBA/AXI bus architecture, pipelining, finite state machines (FSMs), and digital design principles.
• Excellent analytical problem-solving skills and good mathematical skills.
• Strong understanding of timing paths, CDC, and Static Timing Analysis (STA).
• Experience in RTL simulation and verification.
• Knowledge of AMD, Intel (Altera), Microchip, and Lattice FPGA/SoC architectures and proficiency with their respective development tools.
• Exposure to AMD Zynq SoCs, ARM processing systems, and AMBA/AXI bus architecture.
• Proficiency in improving speed, power and area efficiency of RTL designs, and integration of IP cores.
• Experience in standard serial interfaces like I2C, SPI, UART.
• Exposure to high-speed interfaces and controllers such as MIPI CSI/DSI, DDR, PCIe, USB, Ethernet, and LVDS/Sub-LVDS.
• Familiarity with scripting for automation (Tcl , Python) and version control systems (Git).
• Hands-on experience with lab test equipment like logic analyzers, MSO, and on-chip debug.
• Basic knowledge in digital and analog electronics and ability to read circuit schematics.

Desired Qualifications

• Basic understanding in digital image/video processing or hardware DSP pipelines.
• Programming skill in Python, Matlab, C++ etc for software simulation before RTL implementation.

Experience - 3 Years+