Senior RTL Verification and DFT Engineer

Broadcom; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Broadcom Central Engineering is seeking a Staff Engineer with multi-skilled RTL and verification expertise plus DFT capabilities. The role focuses on RTL, verification, and BIST for complex memory and IO subsystems.

You will work across domains using OVM/UVM methodologies to sign off designs with timing, power, and cross-clock checks. Senior-level responsibilities include leading verification efforts, developing robust test benches, and applying MBIST/ATPG/RSQ techniques to ensure reliable

Qualifications

• Hands-on RTL design and verification expertise.
• Familiarity with DFT flows including MBIST, ATPG, RSQ and sign-off.
• Experience with verification methodologies and best practices for DFT signoff.

Responsibilities

• RTL development and verification for Digital subsystems, Memory subsystems including BIST.
• Memory Digital Subsystems with Tessent/Embedded MBIST MBIST, ATPG, RSQ Verification and sign-off.
• Formal verification, Cross Clock Domain checks, Power/Timing sign off Verify complex Digital subsystems through OVM, UVM methodology.

Skills

RTL design

Verification

DFT

Tools

Spyglass

LEC

CDC

DC Ultra

Fusion Compiler

Verilog NC

Verilog XL

UVM

OVM

ATPG

RSQ

Job description

Staff Engineer

Broadcom Central Engineering team is looking for a Multi Skilled RTL, Verification engineer with DFT expertise. The Successful candidate will work in one or more domains of RTL, Verification, DFT for Complex Memory, IO subsystems, Hierarchical Blocks including BIST. It is a great opportunity and challenging role for the people who want to gain in-depth knowledge on end to end chip development flow with deeper expertise on RTL, Synth and Memory BIST.

Responsibilities

• RTL development and Verification for Digital subsystems, Memory Subsystems including BIST.
• Memory Digital Subsystems with Tessent/Embedded MBIST MBIST, ATPG, RSQ Verification and sign-off.
• Formal verification, Cross Clock Domain checks, Power/Timing sign off Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently.

Requirements

Hands on Experience with RTL, Synthesis, Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the DFT signoff. Familiarity with Spyglass, LEC, CDC, and Synthesis tools DC Ultra, Fusion Compiler. Familiarity with GLS, simulation, UVM, OVM methodologies is a big plus Proficiency with Verilog NC, Verilog XL tools Strong fundamentals in digital design and Coding/Verifying complex RTL subsystems

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Experience Level Senior Level