Principal Engineer, Verification

Microchip Technology Inc.; Hyderabad; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Microchip Technology Inc. in Hyderabad is seeking an experienced verification professional to define and develop verification environments for complex SoCs.

You will write verification plans, generate test benches, and implement automatic regression strategies to ensure thorough coverage. You will oversee verification architecture, run simulations and debugging, complete block- and chip-level verification, and collaborate with cross-functional teams to validate design intent and resolve issues

Qualifications

• 8+ years of silicon design or verification experience
• Hands-on experience with OVM/UVM
• Experience with AXI/AHB/DDR/PCIe protocol knowledge
• Coverage/assertion-driven verification experience
• Knowledge of CMOS logic and IC design/development flow
• Proficiency in HDL languages SystemVerilog, Verilog, and VHDL
• UNIX shell scripting, Perl, and Tcl scripting
• Strong English communication and cross‑team collaboration

Responsibilities

• Define and develop verification environments
• Write verification plans and documentation
• Generate test benches and automatic regression plans
• Oversee verification architecture, simulations, debugging of circuit and logic designs
• Complete block-level verification and chip-level verification
• Bring a self‑motivated and enthusiastic approach to meet new requirements
• Work independently handling complex SoC verification platform
• Debug RTL and interface with cross‑functional teams on verification activities

Skills

OVM/UVM

SystemVerilog

Verilog

VHDL

Test bench development

Verification planning

CMOS logic

Unix scripting

Perl

Tcl scripting

English communication

Independent work

Education

Bachelor's in Electrical Engineering

MS in EE or related

Tools

Schematic capture

Simulation tools

Design verification tools

Job description

Responsibilities

• Define and develop verification environments
• Write verification plans and documentation
• Generate test bench and automatic regression plans
• Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs
• Complete block-level verification and chip-level verification
• Bring a self‑motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
• Work mostly independently and handle complex SoC verification platform
• Debug RTL for design intent and interface with cross‑functional teams to collaborate on all verification related activities

Qualifications

• Minimum of 8 years of proven silicon design or verification work experience
• Hands‑on project experience with leading‑edge verification methodologies like OVM/UVM
• One of the protocol knowledge areas AXI/AHB/DDR/PCIe is required
• Hands‑on project experience in coverage/assertion‑driven verification
• Knowledge of IC chip design, development flow, process, and methodology
• Knowledge of CMOS logic design, circuit design, and circuit analysis
• Proficient in HDL languages SystemVerilog, Verilog, and VHDL
• Good knowledge of UNIX shell scripting, Perl, and Tcl scripting
• Good knowledge and understanding of CMOS device operation and characteristics
• Proven experience in writing verification plans, test bench development, simulation, and debugging
• Proficient with UNIX environment and CAE/CAD tools such as schematic capture, simulation, and design verification
• Must be able to learn new technology
• Good analytical and problem‑solving skills
• Excellent written and verbal communication in English
• Experience dealing with and communicating at different levels of the organization

Travel

0% - 25%