Rtl Design Engineer

Acesoft Labs; Bengaluru; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

Acesoft Labs in Bengaluru requires a mid-senior Digital RTL Design Engineer for on-site work. You will design and implement digital RTL for complex systems, and collaborate with verification teams to ensure functional and performance targets are met.

You will perform synthesis, timing analysis, and optimization to meet design specs, debug issues, and participate in design reviews. A Bachelor's or Master's in Electrical Engineering and 4–7 years in RTL design are expected.

Qualifications

• Bachelor's or Master's in Electrical Engineering required.
• 4–7 years of digital RTL design experience.
• Proficiency in Verilog and SystemVerilog.
• Experience with Cadence or Synopsys design tools is preferred.

Responsibilities

• Design and implement digital RTL for complex systems.
• Collaborate with verification engineers to meet functional and performance requirements.
• Perform synthesis, timing analysis, and optimization to meet design specs.
• Debug and resolve design issues, ensuring high-quality designs.
• Participate in design reviews and document methodologies.
• Coordinate with DFT, PD, DV teams for integration and sign-off.

Skills

Verilog

SystemVerilog

Digital RTL design

Timing analysis

Debugging

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence

Synopsys

Job description

Job details:

Job Title: Digital RTL Design Engineer

Location: On-Site

Experience Level: Mid-Senior (3-7 years)

Job Description: Responsibilities:

• Design and implement digital RTL for complex systems.
• Collaborate with verification engineers to ensure design meets all functional and performance requirements.
• Perform synthesis, timing analysis, and optimization to meet design specifications.
• Debug and resolve design issues, ensuring high-quality and reliable designs.
• Participate in design reviews and provide constructive feedback.
• Document design processes, specifications, and methodologies.
• Work closely with cross-functional teams (DFT, PD, DV) for integration and sign-off.

Requirements:

• Bachelors or Master’s degree in Electrical Engineering.
• Minimum of 4-7 years of experience in digital RTL design.
• Proficiency in Verilog, and System Verilog.
• Experience with industry-standard design tools such as Cadence, Synopsys.
• Strong understanding of digital design principles and RTL coding.
• Excellent problem-solving and debugging skills.
• Experience in clock domain crossing (CDC) and reset domain crossing (RDC).
• Knowledge of scripting languages (e.g., Python, Perl) is a plus.

Preferred Qualifications:

• Experience with low-power design techniques.
• Familiarity with protocols like LP/DDR, AXI, APB, AHB is desirable.