Hardware Design Engineer - 1978

Sunrise Biztech Systems; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is hiring a Hadware Design engineer in Bengaluru to lead timing analysis for complex SoC/ASIC designs. You will own full-chip and block-level timing, develop constraints, perform STA, and collaborate with RTL, CAD, and physical teams.

The role requires 8+ years in ASIC/SoC timing, experience with 7nm/5nm nodes, strong scripting (Tcl, Python), and hands-on use of PrimeTime, Tempus, and Innovus. Remote work not indicated; likely full-time.

Qualifications

• 8+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows.
• Strong experience with full-chip or large-block timing closure in advanced technology nodes such as 7nm, 5nm, 3nm, N3P, N2P, or similar.
• Solid understanding of MMMC timing, SDC constraints, clocking architecture, timing exceptions, CDC implications, and hierarchical signoff.

Responsibilities

• Own full-chip and block-level timing analysis and closure for complex SoC/ASIC designs across multiple modes, corners, and signoff scenarios.
• Develop, validate, and maintain timing constraints/SDC for full-chip integration, IP interfaces, clocking, resets, and timing exceptions.
• Perform STA for setup, hold, recovery/removal, clock gating, async paths, and interface timing.
• Debug and resolve timing violations related to datapath, clock path, crosstalk, noise, OCV/AOCV/POCV, derates, and variation effects.
• Work closely with physical design teams on placement, CTS, routing, extraction, and post-route timing optimization.
• Collaborate with RTL, IP, DFT, clocking, CAD, and integration teams to drive timing closure and signoff readiness.
• Execute timing ECOs with minimal impact to power, performance, area, congestion, and design stability.

Skills

ASIC/SoC timing analysis

STA

timing closure

clocking architecture

timing constraints

scripting (Tcl/Python)

cross-functional collaboration

Education

Bachelors or Masters in Electrical/Electronics Engineering

VLSI

Tools

PrimeTime

Tempus

Fusion Compiler

Innovus

ICC2

StarRC

Quantus

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Hadware Design engineer

Experience: 8 + Years

Location: Bangalore

Full Time Employment/Contractual

Role & responsibilities

Top 3 skills:8+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows.

• Strong experience with full-chip or large-block timing closure in advanced technology nodes such as 7nm, 5nm, 3nm, N3P, N2P, or similar.
• Solid understanding of MMMC timing, SDC constraints, clocking architecture, timing exceptions, CDC implications, and hierarchical signoff.

Key Responsibilities:

• Own full-chip and block-level timing analysis and closure for complex SoC/ASIC designs across multiple modes, corners, and signoff scenarios.
• Develop, validate, and maintain timing constraints/SDC for full-chip integration, IP interfaces, clocking, resets, and timing exceptions.
• Perform STA for setup, hold, recovery/removal, clock gating, async paths, and interface timing.
• Debug and resolve timing violations related to datapath, clock path, crosstalk, noise, OCV/AOCV/POCV, derates, and variation effects.
• Work closely with physical design teams on placement, CTS, routing, extraction, and post-route timing optimization.
• Collaborate with RTL, IP, DFT, clocking, CAD, and integration teams to drive timing closure and signoff readiness.
• Execute timing ECOs with minimal impact to power, performance, area, congestion, and design stability.

Preferred Experience & Qualifications:

• 8+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows.
• Strong experience with full-chip or large-block timing closure in advanced technology nodes such as 7nm, 5nm, 3nm, N3P, N2P, or similar.
• Solid understanding of MMMC timing, SDC constraints, clocking architecture, timing exceptions, CDC implications, and hierarchical signoff.
• Experience with synthesis, place-and-route, CTS, routing, extraction, SI/crosstalk, and signoff timing flows.
• Hands-on experience with industry-standard STA/implementation tools such as PrimeTime, Tempus, Fusion Compiler, Innovus, ICC2, StarRC, Quantus, or equivalent.
• Familiarity with high-performance design domains such as CPU, GPU, AI accelerator, fabric/interconnect, PCIe, DDR, multimedia, or memory subsystems is preferred.
• Strong scripting skills in Tcl, Python, Perl, or shell for timing analysis, automation, and report generation.
• Strong problem-solving, communication, and cross-functional collaboration skills.

Preferred candidate profile

Bachelors or Masters degree in Electrical/Electronics Engineering, VLSI, Microelectronics, Computer Engineering, or related field.