STA Engineer Timing Constraints & Closure

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Bangalore is urgently hiring an Engineering - Hardware Design Engineer 2 for a 12-month assignment.

The role focuses on timing constraints for IPs, blocks and full-chip flows, and requires strong TCL scripting and experience with industry-standard EDA tools. You will analyze timing reports, address design and constraint issues, and work with SDC, OCV, AOCV/POCV analyses to ensure timing signoff at GHz-range blocks and subsystems.

Qualifications

• 4-5 years of experience in timing constraints for IPs, blocks and full-chip implementation in flat/hierarchical flows.
• Experience with analyzing timing reports and identifying design and constraint issues.
• Preferred EDA tools: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker.
• Experience in timing closure of high frequency blocks & subsystems (> GHz range).
• Good understanding of DFT modes requirements for timing signoff.
• Good understanding of SDC constraints, OCV, AOCV, POCV analysis.
• Strong TCL/scripting knowledge is mandatory.

Skills

Timing constraints

Timing reports analysis

TCL scripting

GHz timing closure

DFT timing signoff

SDC constraints

OCV/AOCV/POCV analysis

GHZ-range blocks

Tools

Synopsys Design Compiler

PrimeTime

SpyGlass

Fishtail

Tweaker

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading Manufacturing client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title: Engineering - Hardware Design Engineer 2

Location: Bangalore

Duration: 12 Months

Preferred experience:

• 4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
• Experience in timing closure of high frequency blocks & subsystems (> Ghz range )
• Good Understanding of DFT modes requirements for timing signoff
• Good understanding of SDC constraints, OCV, AOCV, POCV analysis.
• Strong TCL/scripting knowledge is mandatory.