Staff Engineer - STA

Bitsilica; Bengaluru; Sur place; INR 2 500 000 - 4 500 000; Plein temps

Résumé du poste

Bitsilica in Bengaluru seeks an experienced Static Timing Analysis (STA) Engineer to own timing sign-off for complex SoC designs, collaborating with PD and RTL teams.

You will drive clock tree and timing path analysis, develop timing constraints (SDC), and support ECO and tape-out sign-off across corners and modes.

Qualifications

• Perform block and full-chip STA for complex SoC designs.
• Develop and validate timing constraints (SDC).
• Drive timing closure across corners and modes.
• Analyze and debug setup/hold violations.
• Work with Physical Design, RTL and Architecture teams.
• Support ECO implementation for timing fixes.
• Handle timing sign-off for tape-out.
• Clock tree and timing path analysis expertise.
• Strong understanding of timing constraints and sign-off flows.
• Experience with advanced technology nodes.

Responsabilités

• Perform block and full-chip STA for complex SoC designs.
• Develop and validate timing constraints (SDC).
• Drive timing closure across corners and modes.
• Analyze and debug setup/hold violations.
• Collaborate with PD, RTL and Architecture teams.
• Support ECO implementation for timing fixes.
• Handle timing sign-off for tape-out.
• Perform clock tree and timing path analysis.
• Contribute to timing closure and sign-off processes.

Connaissances

STA/Timing Analysis

Timing closure

Timing sign-off

SDC/Constraints development

Clocking architecture

CDC concepts

Debugging

Independent work

Problem solving

PD/RTL collaboration

ECO implementation

Sign-off flow experience

Tape-out timing sign-off

Path/Tree analysis

Advanced technology nodes

SYNOPSIS PrimeTime

Synthesis and PD flow

Outils

PrimeTime

Description du poste

Notice Period: Immediate to 30 Days Preferred

We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing sign-off for complex SoC designs. The candidate should have hands‑on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.

• Perform block and full-chip Static Timing Analysis for complex SoC designs
• Develop and validate timing constraints (SDC)
• Drive timing closure across different corners and modes
• Analyze and debug setup/hold violations
• Work closely with Physical Design, RTL, and Architecture teams
• Support ECO implementation for timing fixes
• Handle timing sign-off for tape‑out
• Perform clock tree and timing path analysis
• Strong expertise in Static Timing Analysis (STA)
• Hands‑on experience with SYNOPSIS PrimeTime
• Strong understanding of timing constraints (SDC)
• Experience in timing closure and sign-off
• Understanding of clocking architecture and CDC concepts
• Exposure to advanced technology nodes
• Good understanding of Physical Design flow

Good to Have

• Experience with CPU/GPU or high-performance SoC designs
• Knowledge of Low Power (UPF/CPF)
• Exposure to Synthesis and PD flow
• Experience in ECO and sign-off flows
• 10+ years of experience in STA / Timing Analysis
• Strong debugging and problem‑solving skills
• Ability to work independently and drive timing closure