STA & Synthesis Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 4,200,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks experienced STA & Synthesis Engineers to optimize complex ASIC/SoC designs. You will drive sign-off STA, RTL synthesis, and timing closure across advanced nodes.

You will develop SDC constraints, analyze timing reports, collaborate with RTL and Physical Design teams, and contribute to PPA optimization and design checks. Five to twelve years of hands-on expertise required, with scripting in Tcl and Python beneficial.

Qualifications

• Hands-on STA and RTL synthesis experience.
• Experience with SDC development and timing report analysis.
• Familiarity with MMMC timing analysis and sign-off methodologies.
• Knowledge of EDA tool flows and technology constraints.
• Proficient in Tcl scripting; Python/Perl is a plus.

Responsibilities

• Execute RTL synthesis, timing analysis, and optimization for block-level and full-chip ASIC/SoC designs.
• Perform sign-off STA including setup/hold analysis and timing exception validation.
• Develop, review, and debug timing constraints using SDCs and clocks.
• Drive timing closure through synthesis optimization and coordination with Physical Design.
• Analyze timing reports, identify critical paths, and resolve violations across PVT corners.
• Work on synthesis QoR optimization for timing, power, and area (PPA).
• Perform design checks for unconstrained paths and clock-domain interactions.
• Collaborate with RTL, Physical Design, DFT, and design methodology teams.

Skills

STA

RTL Synthesis

Timing constraints

SDC development

Tcl scripting

Python

MMM C timing

PPA optimization

Education

Bachelor's/Master's in Electronics / Electrical Engineering or related

Job description

We are looking for experienced STA & Synthesis Engineers with strong expertise in static timing analysis, RTL synthesis, timing closure, and design optimization for complex ASIC/SoC designs. The ideal candidate should have hands-on experience in sign-off STA, synthesis flows, timing constraints, and PPA optimization across advanced technology nodes.

Key Responsibilities:

• Execute RTL synthesis, timing analysis, and optimization for block-level and/or full-chip ASIC/SoC designs.
• Perform sign-off Static Timing Analysis (STA), including setup/hold analysis, recovery/removal checks, and timing exception validation.
• Develop, review, and debug timing constraints using SDC, including clocks, generated clocks, false paths, and multicycle paths.
• Drive timing closure through synthesis optimization, logic restructuring, and coordination with Physical Design teams.
• Analyze timing reports, identify critical paths, and resolve timing violations across PVT corners and operating modes.
• Work on synthesis QoR optimization for timing, power, and area (PPA).
• Perform design checks covering unconstrained paths, clock-domain interactions, and timing consistency.
• Collaborate with RTL, Physical Design, DFT, and design methodology teams to improve implementation quality.
• Support multi-mode, multi-corner (MMMC) timing analysis and sign-off activities.

Required Technical Skills:

• Strong hands-on experience in Static Timing Analysis (STA) and/or RTL Synthesis.
• Expertise in timing constraints, SDC development, and timing report analysis.
• Experience with industry-standard EDA tools such as:
• Strong understanding of setup/hold timing, clock uncertainty, skew, latency, OCV/AOCV/POCV, and timing derates.
• Knowledge of ASIC/SoC design flows, standard-cell libraries, and technology constraints.
• Experience with timing optimization, synthesis QoR analysis, and PPA trade-offs.
• Familiarity with Tcl scripting and automation; Perl or Python is an advantage.
• Understanding of multi-mode, multi-corner (MMMC) analysis and sign-off methodologies.

Preferred Qualifications:

• Experience with advanced technology nodes and complex SoC designs.
• Exposure to post-synthesis and post-route timing analysis.
• Knowledge of low-power design techniques, clock gating, and timing-aware synthesis.
• Experience with ECO implementation and timing convergence.
• Strong debugging, analytical, and cross-functional collaboration skills.

Candidate Profile:

• Experience: 5–12 years in VLSI/ASIC design implementation.
• Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or a related discipline.
• Must have strong hands-on technical expertise in STA, synthesis, or both, depending on the assigned position.