STA/Synthesis Engineer - Kochi

N Human Resources & Management Systems; Ernakulam; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

N Human Resources & Management Systems in India is hiring a STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

The role requires 4+ years of hands-on STA and Synthesis experience, strong TCL scripting, and Unix environment skills, with a focus on timing closure across corners and modes and collaboration with RTL and Physical Design teams.

Qualifications

• 4+ years of hands-on STA and Synthesis experience.
• Strong TCL scripting in a Unix environment.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Own synthesis and static timing analysis across design blocks.
• Drive timing signoff from RTL through tapeout.
• Perform logic-aware synthesis, LEC, and VCLP signoff.
• Develop SDC and UPF constraints including DFT-aware constraints.
• Lead pre- and post-layout timing closure across corners and modes.
• Manual ECO generation to resolve timing and DRC violations.
• Collaborate with RTL design and Physical Design teams on SoC timing closure.

Skills

TCL scripting

Unix environment

timing signoff flows

Synthesis

Job description

N Human Resources & Management Systems | Full time

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• - Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• - SDC and UPF constraint development, including DFT-aware constraints
• - Pre- and post-layout timing closure across corners and modes
• - Manual ECO generation to resolve timing and DRC violations
• - Timing closure at block, subsystem and full-chip level
• - Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• - Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• - 4+ years of hands-on experience in STA and Synthesis
• - Strong TCL scripting and Unix environment skills
• - Comprehensive knowledge of timing signoff flows and constraint development