STA Synthesis Engineer - Kochi

n Human Resources & Management Systems [ nHRMS ]; Ernakulam; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

n Human Resources & Management Systems [ nHRMS ] is seeking an STA/Synthesis Engineer to own synthesis and timing signoff from RTL to tapeout, joining our VLSI delivery team in India. You will drive timing closure, develop SDC/UPF constraints, and mentor a small team of engineers to ensure robust STA practices.

The role requires 4+ years in STA/Synthesis, strong TCL scripting, and deep knowledge of timing signoff flows.

Qualifications

• 4+ years of hands-on experience in STA and Synthesis.
• Strong TCL scripting and Unix environment skills.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices.
• Partner with RTL design and Physical Design teams on SoC timing closure.
• Develop constraints (SDC/UPF) including DFT-aware constraints.
• Perform pre- and post-layout timing closure across corners and modes.
• Generate ECOs to resolve timing and DRC violations.

Skills

STA & Synthesis

Team leadership

Timing signoff flows

RTL design collaboration

Tools

TCL scripting

Unix

SDC/UPF constraints

Job description

Job Description:

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities

• Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• SDC and UPF constraint development, including DFT-aware constraints
• Pre- and post-layout timing closure across corners and modes
• Manual ECO generation to resolve timing and DRC violations
• Timing closure at block, subsystem and full-chip level
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements

• 4+ years of hands-on experience in STA and Synthesis
• Strong TCL scripting and Unix environment skills
• Comprehensive knowledge of timing signoff flows and constraint development

Requirements