STA Synthesis Engineer - Coimbatore

n Human Resources & Management Systems [ nHRMS ]; Coimbatore District; On-site; INR 900,000 - 1,300,000; Full time

Job summary

nHRMS is seeking an STA/Synthesis Engineer to join our VLSI delivery team in India. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

You will lead a small team of 4-5 engineers and collaborate closely with RTL design and Physical Design teams to achieve robust SoC timing closure.

Qualifications

• 4+ years of hands-on STA and Synthesis experience.
• Strong TCL scripting and Unix environment skills.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Logic-aware synthesis, LEC, and VCLP signoff
• SDC and UPF constraint development, including DFT constraints
• Pre- and post-layout timing closure across corners and modes
• Manual ECO generation to resolve timing and DRC violations
• Timing closure at block, subsystem and full-chip level
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner with RTL design and Physical Design teams on SoC timing closure

Skills

STA

Synthesis

Timing analysis

TCL scripting

Unix

Timing signoff

Job description

Job Description:

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• - Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff


• - SDC and UPF constraint development, including DFT-aware constraints


• - Pre- and post-layout timing closure across corners and modes


• - Manual ECO generation to resolve timing and DRC violations


• - Timing closure at block, subsystem and full-chip level


• - Lead and mentor a team of 4-5 engineers on STA/Synthesis practices


• - Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• - 4+ years of hands-on experience in STA and Synthesis


• - Strong TCL scripting and Unix environment skills


• - Comprehensive knowledge of timing signoff flows and constraint development