STA Synthesis Engineer - Ahmedabad

n Human Resources & Management Systems [ nHRMS ]; Ahmedabad District; On-site; INR 900,000 - 1,500,000; Full time

Job summary

nHRMS is seeking an STA/Synthesis Engineer to own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout. You will lead a small team and collaborate with RTL and Physical Design teams on SoC timing closure.

The role requires hands-on experience in STA and Synthesis, strong TCL scripting, and Unix expertise, with a deep understanding of timing signoff flows and constraint development.

Qualifications

• 4+ years hands-on experience in STA and Synthesis.
• Strong TCL scripting and Unix environment skills.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Own logic-aware synthesis, LE C and VCLP signoff.
• Develop and maintain SDC and UPF constraints, including DFT-aware constraints.
• Perform pre- and post-layout timing closure across corners and modes.
• Generate manual ECOs to resolve timing and DRC violations.
• Achieve timing closure at block, subsystem and full-chip levels.
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices.
• Collaborate closely with RTL design and Physical Design teams on SoC timing closure.

Skills

STA

Synthesis

TCL scripting

Unix

Timing signoff

Job description

Job Description:

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• - Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff


• - SDC and UPF constraint development, including DFT-aware constraints


• - Pre- and post-layout timing closure across corners and modes


• - Manual ECO generation to resolve timing and DRC violations


• - Timing closure at block, subsystem and full-chip level


• - Lead and mentor a team of 4-5 engineers on STA/Synthesis practices


• - Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• - 4+ years of hands-on experience in STA and Synthesis


• - Strong TCL scripting and Unix environment skills


• - Comprehensive knowledge of timing signoff flows and constraint development