STA Synthesis Engineer - Chennai

n Human Resources & Management Systems [ nHRMS ]; Chennai District; On-site; INR 900,000 - 1,500,000; Full time

Job summary

nHRMS is seeking an STA/Synthesis Engineer to join our VLSI delivery team in Chennai. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

You will perform logic-aware synthesis, LEC, and VCLP signoff, and develop SDC/UPF constraints including DFT-aware constraints. Lead 4–5 engineers and collaborate closely with RTL design and Physical Design teams for tight SoC timing closure.

Qualifications

• 4+ years of hands-on experience in STA and Synthesis.
• Strong TCL scripting and Unix environment skills.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Own synthesis and STA across design blocks and drive timing signoff from RTL through tapeout.
• Perform logic-aware synthesis, LEC, and VCLP signoff; develop constraints (SDC/UPF) including DFT-aware constraints.
• Conduct pre- and post-layout timing closure across corners and modes; generate ECOs to fix timing/DRC issues.
• Lead and mentor a team of 4–5 engineers on STA/Synthesis practices; collaborate with RTL and PD teams for SoC timing closure.

Skills

STA

Synthesis

TCL scripting

Unix environment

Timing signoff

Mentoring

Job description

Job Description

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities

• Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• SDC and UPF constraint development, including DFT-aware constraints
• Pre- and post-layout timing closure across corners and modes
• Manual ECO generation to resolve timing and DRC violations
• Timing closure at block, subsystem and full-chip level
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements

• 4+ years of hands-on experience in STA and Synthesis
• Strong TCL scripting and Unix environment skills
• Comprehensive knowledge of timing signoff flows and constraint development