STA (STATIC TIMING ANALYSIS) ENGINEER - VLSI

Shashwath Solution; Bengaluru; On-site; INR 1,400,000 - 2,600,000; Full time

Job summary

Shashwath Solution Bengaluru is seeking a Timing Analyst to join the hardware team. You will work closely with design and implementation teams to develop and qualify timing constraints, perform block and SoC level timing analysis, and sign off using industry tools such as Primetime and Tempus.

The role requires hands-on scripting with TCL/Perl, knowledge of SDC syntax, and experience with cross-corner timing, MMMC, and timing ECOs for multi-voltage designs.

Qualifications

• Strong understanding of timing concepts.
• Experience in timing analysis at block and SoC level.
• Proficient with Primetime/Tempus for timing signoff.
• Experience with DMSA or Tweaker.
• Knowledge of timing modes and corners.
• Experience with MMMC.
• Hands-on scripting with TCL or Perl.
• Work with physical design to resolve timing issues.
• Plan, track, and report self-execution results.
• Close timing challenges by manually closing difficult paths.

Responsibilities

• Should have understanding of SDC and constraints syntax
• Work with the design and implementation teams to develop and qualify timing constraints
• Experience in Timing Analysis both at block level and SoC level
• Experience with Industry Timing signoff tools like Primetime / Tempus is a must
• Experience in DMSA or Tweaker
• Should have understanding of different Timing modes and Corners
• Experience in MMMC
• Work closely with the physical design engineers to resolve implementation related timing issues
• Should be able to plan and track self execution and report result on regular basis systematically
• Should be able to solve timing challenges in Block/SOC by manually closing difficult paths
• Should have a clear understanding of Crosstalk delay/noise, Timing derates, AOCV/POCV concepts and its impact of design closure
• Should have worked on Timing ECO generation in multi-voltage designs
• Experience Timing & Noise Signoff Closure at block level or Full chip-level on advanced process nodes
• Hands on scripting skills on TCL / Perl

Skills

Timing concepts

Timing analysis

Scripting

Tools

Primetime

Tempus

DMSA

Tweaker

TCL

Perl

Job description

Job Summary

Very good understanding of timing concepts

Responsibilities

• Should have understanding of SDC and constraints syntax


• Work with the design and implementation teams to develop and qualify timing constraints


• Experience in Timing Analysis both at block level and SoC level


• Experience with Industry Timing signoff tools like Primetime / Tempus is a must


• Experience in DMSA or Tweaker


• Should have understanding of different Timing modes and Corners


• Experience in MMMC


• Work closely with the physical design engineers to resolve implementation related timing issues


• Should be able to plan and track self execution and report result on regular basis systematically


• Should be able to solve timing challenges in Block/SOC by manually closing difficult paths


• Should have a clear understanding of Crosstalk delay/noise, Timing derates, AOCV/POCV concepts and its impact of design closure


• Should have worked on Timing ECO generation in multi-voltage designs


• Experience Timing & Noise Signoff Closure at block level or Full chip-level on advanced process nodes


• Hands on scripting skills on TCL / Perl