STA (STATIC TIMING ANALYSIS) ENGINEERS | VLSI

Shashwath Solution; Dadri; On-site; INR 1,000,000 - 1,600,000; Full time

Job summary

Shashwath Solution is seeking a Timing Analysis Engineer in Uttar Pradesh, India. The role focuses on developing and qualifying timing constraints, working with design and physical design teams to resolve timing issues, and ensuring timely timing closure for blocks and full chips in multi-voltage designs.

The ideal candidate will have hands-on experience with SDC syntax, industry timing signoff tools such as Primetime and Tempus, and knowledge of MMMC.

Qualifications

• Strong hands-on experience with timing analysis at block and SoC level.
• Deep understanding of SDC and constraints syntax.
• Experience with industry timing signoff tools (Primetime/Tempus) is essential.
• Familiarity with timing closure in multi-voltage designs and ECO generation.
• Experience with Timing & Noise Signoff Closure at block or full-chip level.

Responsibilities

• Work with design and implementation teams to develop and qualify timing constraints.
• Collaborate with physical design engineers to resolve timing-related issues.
• Plan and track self execution and report results regularly.
• Solve timing challenges in blocks/SoC by closing difficult paths manually.

Skills

Timing analysis

SDC syntax

Constraints syntax

Tools

Primetime

Tempus

DMSA

Tweaker

MMMC

Job description

Job Summary

Very good understanding of timing concepts

Responsibilities

• Work with the design and implementation teams to develop and qualify timing constraints
• Work closely with the physical design engineers to resolve implementation related timing issues
• Should be able to plan and track self execution and report result on regular basis systematically
• Should be able to solve timing challenges in Block/SOC by manually closing difficult paths

Requirements

• Should have understanding of SDC and constraints syntax
• Experience in Timing Analysis both at block level and SoC level
• Experience with Industry Timing signoff tools like Primetime / Tempus is a must
• Experience in DMSA or Tweaker
• Should have understanding of different Timing modes and Corners
• Experience in MMMC
• Should have worked on Timing ECO generation in multi-voltage designs
• Experience Timing & Noise Signoff Closure at block level or Full chip-level on advanced process nodes