Lead Static Timing Analysis (STA) Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 5,400,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks an experienced Static Timing Analysis (STA) Engineer to own timing sign-off and closure for complex ICs/SoCs. You will define timing constraints, perform MMMC timing analysis, and collaborate with design and physical teams to meet target frequency.

The role requires hands-on experience with sign-off workflows, SDC constraints, and flow automation. Proficiency with Synopsys Fusion Compiler, ICC2, Primetime, Innovus, or Mentor tools is expected,

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, or related field.

Responsibilities

• Timing Sign-off and Analysis: own timing sign-off for blocks, sub-systems, and full chip.
• Timing Closure Ownership: drive timing closure from pre-layout to post-layout.
• Constraint Management: develop, validate, and maintain SDC and timing constraints for all modes.
• MMMC Analysis: perform timing across multiple corners and modes.
• Critical Path Identification: analyze reports to identify & debug critical paths and resolve violations.
• Signal Integrity & Noise: incorporate OCV, crosstalk, and IR-drop aware STA into sign-off.

Skills

STA experience

Timing analysis

Sign-off ownership

Scripting

Education

Electrical Engineering (EE)

VLSI

Tools

Fusion Compiler

ICC2

Primetime

Innovus

Mentor Graphics

Job description

Lead Static Timing Analysis (STA) Engineer

Experience: 6 to 10 years of experience in STA.

Job Summary

The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.

Key Responsibilities

• Timing Sign-off and Analysis
• Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.
• Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).
• MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).
• Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations.
• Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.

Methodology and Flow

• Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.
• Automate repetitive tasks and report generation using scripting languages.
• Generate final timing reports and sign-off collateral for tape-out.

Education

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills

• EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.