Sta Engineer

Mirafra; Karnataka; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Mirafra in India seeks an STA Engineer to perform Static Timing Analysis at block and full-chip levels, coordinating with RTL and Physical Design teams to ensure timing closure across multiple corners.

The role requires hands-on PrimeTime experience, strong knowledge of SDC constraints, and solid debugging and collaboration skills.

Location: Bangalore/Noida; experience 3–8 years; BE/BTech or ME/MTech in Electronics/VLSI. Opportunity to grow within a dynamic VLSI group.

Qualifications

• Strong understanding of Static Timing Analysis concepts.
• Hands-on experience with Synopsys PrimeTime.
• Good knowledge of SDC constraints and timing exceptions.
• Experience with setup/hold analysis and timing closure.
• Knowledge of MCMM analysis and PVT corners.
• Understanding of clock definitions, generated clocks, false paths and multicycle paths.
• Basic TCL scripting skills.
• Knowledge of signal integrity and crosstalk analysis is an added advantage.

Responsibilities

• Perform Static Timing Analysis (STA) at block and full-chip levels.
• Analyze setup, hold, recovery and removal timing violations.
• Develop, validate and debug timing constraints (SDC).
• Perform timing analysis across multiple PVT corners and operating modes (MCMM).
• Identify critical timing paths and recommend optimization solutions.
• Work on timing closure in coordination with Physical Design and RTL teams.
• Analyze timing reports and debug timing issues.
• Perform pre-layout and post-layout timing analysis.
• Ensure design meets timing requirements across all modes and corners.

Skills

Static Timing Analysis

Synopsys PrimeTime

SDC constraints

MCMM analysis

PVT corners

Clock definitions

Generated clocks

False paths

Multicycle paths

TCL scripting

Signal integrity awareness

Education

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI or related disciplines

Job description

Job Description STA Engineer (Static Timing Analysis)

Job Title: STA Engineer Experience: 3–8 Years Domain: VLSI / Semiconductor Location: Bangalore / Noida

Key Responsibilities

• Perform Static Timing Analysis (STA) at block and full-chip levels.
• Analyze setup, hold, recovery and removal timing violations.
• Develop, validate and debug timing constraints (SDC).
• Perform timing analysis across multiple PVT corners and operating modes (MCMM).
• Identify critical timing paths and recommend optimization solutions.
• Work on timing closure in coordination with Physical Design and RTL teams.
• Analyze timing reports and debug timing issues.
• Perform pre-layout and post-layout timing analysis.
• Ensure design meets timing requirements across all modes and corners.

Required Technical Skills

• Strong understanding of Static Timing Analysis concepts.
• Hands-on experience with Synopsys PrimeTime.
• Good knowledge of SDC constraints and timing exceptions.
• Experience with setup/hold analysis and timing closure.
• Knowledge of MCMM analysis and PVT corners.
• Understanding of clock definitions, generated clocks, false paths and multicycle paths.
• Basic TCL scripting skills.
• Knowledge of signal integrity and crosstalk analysis is an added advantage.

Educational Qualification

- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI or related disciplines.

Preferred Candidate Profile

• Strong debugging and analytical skills.
• Hands-on experience in STA flows.
• Good understanding of digital design and physical design concepts.
• Ability to collaborate with cross-functional VLSI teams.