STA engineer

Proxelera; Hyderabad, Bengaluru; On-site; INR 2,000,000 - 4,000,000; Full time

Job summary

Proxelera PVT LTD in India seeks an experienced timing engineer with strong STA concepts and timing constraints expertise across SoC and block levels. You will debug timing issues and contribute to timing constraints development.

The role offers exposure to IP timing constraints, integration into SoC flows, and collaboration with RTL and physical design teams to ensure reliable timing closure.

Qualifications

• Understanding of STA concepts and timing constraints within VLSI design flow.
• Experience with Verilog, timing (.lib), LEF, and GDS; familiarity with PD verification (DRC/LVS).
• Ability to write/modify scripts in Perl, Unix shell, Tcl, or Python.

Responsibilities

• Understand timing constraints and verify them at SoC and block level, debugging timing issues.
• Expose timing constraints development for SoC and block level.
• Promote IP timing constraints to SoC level and integrate them into SoC timing constraints.

Skills

STA concepts

Timing constraints

Verilog

Scripting

Physical design

DRC/LVS familiarity

LEF/GDS familiarity

Tools

LEF

GDS

Perl

Unix shell

Job description

The Job Role:

• We are looking for profiles with strong understanding of STA concepts and Timing constraints with 6-15 years of experience

Job Responsibility:

• Must have solid understanding of timing constraints and their verification at SoC and block level along with good understanding of STA concepts to debug timing constraint issues.
• This role will provide SoC and block level timing constraints development exposure.
• Responsibilities will include promotion of multiple IP timing constraints' to SoC level and integrating them into SoC timing constraints.

Required Skills:

• Understanding of STA concepts and Timing constraints as well as VLSI design flow;
• Familiarity with Verilog, timing (.lib), LEF, GDS; Familiarity with physical design verification, e.g. DRC and LVS; Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language. 3-6 years of experience