Sr Manager / Director - Physical Design

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bangalore Rural; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

SignOff Semiconductors Pvt. Ltd. is seeking a Sr Manager/Director to lead global physical design and CAD teams from Bangalore North. You will own full-chip and large-block physical implementation, including floorplanning, placement, CTS, routing, and congestion analysis.

The role requires 12–20 years in ASIC/SoC design with at least 2+ years in a senior management capacity, and hands-on experience with Synopsys or Cadence.

Qualifications

• 12-20 years in ASIC/SoC physical design and timing signoff, with at least 2+ years in a senior management or director role.
• Hands-on expertise with advanced technology nodes and EDA tools from vendors like Synopsys or Cadence.
• Deep understanding of low-power architectures (DVFS, power gating), multi-voltage domains, and high-speed interfaces.

Responsibilities

• Leadership & Strategy: Build, mentor, and scale high-performing physical design and CAD teams across global sites.
• Execution & Tape-out: Own full-chip and large block-level physical implementation, handling floorplanning, placement, CTS, routing, and congestion analysis.
• Signoff & Closure: Drive STA, signal integrity, IR drop/EM closure, physical verification (DRC/LVS), and low-power verification.
• Cross-functional Collaboration: Partner with architecture, RTL design, DFT, analog/mixed-signal, and packaging teams.
• Methodology Innovation: Drive EDA tool optimization, advanced packaging/chiplet flows, and AI-driven automation frameworks.

Skills

Leadership

Strategy

Cross-functional Collaboration

EDA Tools

STA

Education

Bachelor's or Master's in Electrical/Electronics/CS

Tools

Synopsys

Cadence

Power/Timing Analysis Tools

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

Sr Manager / Director - Physical Design

Bangalore North, India

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

Key Responsibilities

• Leadership & Strategy: Build, mentor, and scale high-performing physical design and CAD teams across global sites.
  
• Execution & Tape-out: Own full-chip and large block-level physical implementation, handling floorplanning, placement, clock tree synthesis (CTS), routing, and congestion analysis.
  
• Signoff & Closure: Drive static timing analysis (STA), signal integrity, IR drop/electromigration (EM) closure, physical verification (DRC/LVS), and low-power verification (UPF/CPF).
  
• Cross-functional Collaboration: Partner with architecture, RTL design, DFT, analog/mixed-signal, and packaging teams.
  
• Methodology Innovation: Drive EDA tool optimization, advanced packaging/chiplet flows, and AI-driven automation frameworks.
  

Requirements

Requirements & Qualifications

• Experience: 12-20 years in ASIC/SoC physical design and timing signoff, with at least 2+ years in a senior management or director role.
  
• Technical Mastery: Hands-on expertise with advanced technology nodes and EDA tools from vendors like Synopsys or Cadence.
  
• Domain Knowledge: Deep understanding of low-power architectures (DVFS, power gating), multi-voltage domains, and high-speed interfaces.