FCT Engineer

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

SIGNOFF SEMICONDUCTORS PVT. LTD.

in Bengaluru is seeking a Full Chip STA Engineer responsible for end-to-end static timing analysis for complex ASIC/SoC designs, ensuring timing closure across modes and corners. The role requires strong hands-on experience with industry STA tools such as PrimeTime/Tempus, deep knowledge of SDC and timing signoff methodologies, and collaboration with RTL, Synthesis, and Physical Design teams to deliver tape-out-ready designs.

Qualifications

• 3–5 years of Static Timing Analysis experience.
• Full-chip STA experience required.
• Experience on AMD projects is a plus.
• Proficient with PrimeTime/Tempus or equivalents.
• Strong understanding of SDC, MCMM, setup/hold checks, timing signoff methodologies, and ECO-driven timing closure.

Responsibilities

• Perform full-chip timing analysis from early investigation through tape-out.
• Analyze timing across modes and corners.
• Develop, validate, and maintain timing constraints (SDC) for block and full-chip designs.
• Define margin strategies with Synthesis and Design teams.
• Debug timing violations with Physical Design for PnR closure.
• Support timing signoff using PrimeTime/Tempus.
• Analyze setup/hold, clock paths, crosstalk, OCV/AOCV/POCV.
• Collaborate with RTL, Physical Design, DFT, and Synthesis teams to achieve timing closure.
• Prepare timing reports and signoff documentation.

Skills

STA

ASIC closure

Scripting TCL/Python

Cross-functional

Chip design experience

Tools

PrimeTime

Tempus

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

The Full Chip STA Engineer will be responsible for performing end-to-end Static Timing Analysis for complex ASIC and SoC designs, ensuring timing closure across multiple modes and corners.

Responsibilities

• Perform full-chip timing analysis from early investigation through final implementation and tape-out.
• Perform static timing analysis and timing closure across multiple functional and test modes and corners.
• Develop, validate, and maintain timing constraints (SDC) for block and full-chip designs.
• Analyze timing scenarios and define appropriate margin strategies in collaboration with Synthesis and Design teams.
• Partner with Physical Design teams to debug timing violations and close designs through PnR and ECO cycles.
• Support timing signoff using industry-standard STA tools such as PrimeTime, Tempus, or equivalent.
• Analyze setup/hold violations, clock paths, crosstalk, OCV/AOCV/POCV, and signal integrity issues.
• Work closely with RTL, Physical Design, DFT, Synthesis, and other cross-functional teams to achieve timing closure.
• Support development and implementation of timing methodologies and signoff flows.
• Prepare timing reports, signoff documentation, and summaries to support project milestones and tape-out.
  

Requirements

• 3-5 years of relevant experience in Static Timing Analysis (STA).
  
• Full-chip STA experience is mandatory.
  
• Prior experience working on AMD projects/products is highly preferred.
  
• Strong hands-on experience in ASIC timing constraints development, validation, and timing closure.
  
• Proficiency with industry-standard STA tools such as PrimeTime, Tempus, or equivalent.
  
• Solid understanding of SDC, MCMM analysis, setup/hold checks, timing signoff methodologies, and ECO-driven timing closure.
  
• Experience driving timing closure across both functional and test modes.
  
• Good knowledge of deep sub-micron timing challenges, including crosstalk, noise/glitch analysis, OCV/AOCV/POCV, variation-aware timing, and signal integrity.
  
• Working understanding of Physical Design flows, including placement, CTS, routing, PnR, and ECO implementation.
  
• Proficiency in scripting languages such as TCL, Perl, Python, Shell/C-Shell, or Bash for automation and flow development.
  
• Exposure to advanced technology nodes (7nm, 5nm, or below) is a plus.
  
• Strong analytical, debugging, and problem-solving skills with effective written and verbal communication.
  
• Demonstrated ability to collaborate with cross-functional teams and deliver results in a fast-paced project environment.
  
• Self-motivated individual with a strong sense of ownership, accountability, and teamwork.