Physical Design Manager – ASIC/SoC

Best NanoTech; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Best NanoTech is seeking an experienced Physical Design Manager to lead Physical Design and CAD teams for end-to-end ASIC/SoC implementation. You will drive floorplanning, CTS, routing, and signoff while coordinating with Architecture, RTL, DFT, and Packaging groups.

You will mentor leads, manage multi-location teams, and ensure timely tapeouts with a focus on low-power and advanced-node flows.

Qualifications

• B.Tech / M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or related discipline.
• 12-20 years of experience in ASIC/SoC Physical Design and physical implementation.
• Strong experience in STA, timing closure, and physical signoff.
• People management experience is mandatory.
• Minimum 2+ years of experience in a senior management, engineering management, or director-level role.
• Proven ownership of full-chip implementation and successful ASIC/SoC tapeouts.
• Hands-on experience with advanced semiconductor technology nodes.

Responsibilities

• Lead and manage Physical Design and CAD teams across multiple locations.
• Own end-to-end ASIC/SoC physical implementation from netlist to GDSII/tapeout.
• Drive floorplanning, power planning, placement, optimization, CTS, routing, and post-route optimization.
• Lead STA and timing closure across multiple modes and corners.
• Drive physical signoff including signal integrity, IR drop, electromigration, DRC, LVS, and low-power verification.
• Provide technical direction for complex advanced-node ASIC/SoC designs.
• Lead implementation of low-power architectures, including DVFS, power gating, multi-voltage domains, UPF/CPF, and power-aware flows.
• Collaborate with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams to resolve issues.
• Drive EDA methodology, flow development, automation, and tool optimization using Synopsys and/or Cadence platforms.
• Review design quality, implementation metrics, timing, power, area, congestion, and signoff readiness.
• Support advanced packaging and chiplet-based implementation flows where applicable.
• Mentor technical leads and engineers, manage team capacity, and drive execution against project and tapeout schedules.

Skills

ASIC/SoC PD

Floorplanning

Power Planning

Placement & Optimization

CTS

Routing & Post-Route

EM/IR Drop

STA / Timing Closure

Multi-Voltage Domains

Leadership & Mgmt

Education

B.Tech / M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or related discipline

Tools

Synopsys Signoff

Cadence Signoff

Job description

Education: B.Tech / M.Tech in Electronics, Electrical Engineering, VLSI, or related discipline

Role Overview

We are seeking an experienced Physical Design Manager to lead Physical Design and CAD teams responsible for end-to-end ASIC/SoC physical implementation.

The role requires strong technical depth in full-chip Physical Design, advanced technology nodes, STA/timing closure, physical signoff, low-power implementation, and tapeout, combined with proven people-management experience. The position will work closely with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams.

Key Responsibilities

• Lead and manage Physical Design and CAD teams across multiple locations.
• Own end-to-end ASIC/SoC physical implementation from netlist to GDSII/tapeout.
• Drive floorplanning, power planning, placement, optimization, CTS, routing, and post-route optimization.
• Lead STA and timing closure across multiple modes and corners.
• Drive physical signoff including signal integrity, IR drop, electromigration (EM), DRC, LVS, and low-power verification.
• Provide technical direction for complex advanced-node ASIC/SoC designs.
• Lead implementation of low-power architectures, including DVFS, power gating, multi-voltage domains, UPF/CPF, and power-aware flows.
• Collaborate with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams to resolve implementation and integration issues.
• Drive EDA methodology, flow development, automation, and tool optimization using Synopsys and/or Cadence platforms.
• Review design quality, implementation metrics, timing, power, area, congestion, and signoff readiness.
• Support advanced packaging and chiplet-based implementation flows where applicable.
• Mentor technical leads and engineers, manage team capacity, and drive execution against project and tapeout schedules.

Required Qualifications

• B.Tech / M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
• 12 -20 years of experience in ASIC/SoC Physical Design and physical implementation.
• Strong experience in STA, timing closure, and physical signoff.
• People management experience is mandatory.
• Minimum 2+ years of experience in a senior management, engineering management, or director-level role.
• Proven ownership of full-chip implementation and successful ASIC/SoC tapeouts.
• Hands-on experience with advanced semiconductor technology nodes.
• Strong understanding of low-power and multi-voltage SoC implementation.
• Experience managing technically complex projects and cross-functional engineering teams.

Technical Skills

Physical Design

• ASIC/SoC Physical Design
• Floorplanning and Power Planning
• Placement and Optimization
• Clock Tree Synthesis (CTS)
• Routing and Post-Route Optimization
• Full-Chip Physical Implementation
• PPA Optimization
• Congestion Analysis

Timing & Signoff

• Static Timing Analysis (STA)
• Multi-Mode Multi-Corner (MMMC) Analysis
• Timing Closure
• Signal Integrity / Crosstalk
• IR Drop and Electromigration (EM)
• DRC / LVS
• Physical Verification and Signoff

Low-Power Design

• UPF / CPF
• DVFS
• Power Gating
• Multi-Voltage Domains
• Low-Power Implementation and Verification

EDA Tools

• Synopsys Physical Design / Signoff Tool Suite
• Cadence Physical Design / Signoff Tool Suite