Lead Physical Design Engineer

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bengaluru South; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

SignOff Semiconductors in Bengaluru South, India, seeks a Lead Physical Design Engineer to drive RTL-to-GDSII implementation for advanced SoCs. You will lead a team of PD engineers, own tape-out schedules, and ensure timing and power closure across multi‑node processes.

The role requires 7–10+ years in Physical Design with at least 2 years in leadership, deep EDA tool expertise, and strong scripting abilities.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 7–10+ years of hands-on experience in Physical Design, with at least 2+ years acting as a technical lead or manager.
• Proven tape-out experience on FinFET/GAA nodes (7nm/5nm/3nm).
• Strong scripting in TCL, Python, Perl, Make.

Responsibilities

• Technical Leadership: guide and manage a team of physical design engineers and track tape-out schedules.
• End-to-End Implementation: drive Floor planning, Power Grid design, Placement, CTS, and Routing.
• Synthesis & Timing Closure: manage physical synthesis and STA for MMMC timing closure.
• Power & Reliability: perform UPF/CPF, EM/IR-drop analysis, and voltage drop issues.
• Physical Verification: ensure clean DRC, LVS, Antenna, and ERC checks for tape-out readiness.
• Cross-Functional Collaboration: work with RTL, DFT, Custom Layout, and Architecture teams to optimize PPA.
• Flow & Methodology: develop and optimize automation scripts and flows.

Skills

Team Leadership

Problem Solving

Communication

Cross-functional Collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering / Electronics / Computer Engineering

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

Synopsys PrimeTime

Cadence Tempus

Siemens Calibre

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

Lead Physical Design Engineer

Bangalore South, India | Posted on 08/14/2026

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

Here is a comprehensive and standard Job Description (JD) template for a Lead Physical Design Engineer. You can easily copy, paste, and adjust the bracketed information to fit your specific company or team needs.

Job Title: Lead Physical Design Engineer

Location: [City, State / Remote / Hybrid] Department: [Hardware / Silicon Engineering] Reports To: [Director of Physical Design / Engineering Manager]

Role Overview

We are seeking an experienced and highly driven Lead Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs. In this role, you will lead a team of engineers through the entire RTL-to-GDSII lifecycle. You will take ownership of complex block-level and top-level physical design tasks, ensure aggressive timing and power closure, and deliver high-quality tape-outs on advanced technology nodes.

Key Responsibilities

Technical Leadership: Guide, mentor, and manage a team of physical design engineers. Define execution strategies, allocate block-level resources, and track progress against tape-out schedules.

End-to-End Implementation: Drive core physical design activities, including complex Floor planning, Power Grid design, Placement, Clock Tree Synthesis (CTS), and Routing.

Synthesis & Timing Closure: Manage physical synthesis and drive Static Timing Analysis (STA) for rapid timing closure (setup, hold, SI/crosstalk) across multi-mode, multi-corner (MMMC) scenarios.

Power & Reliability: Execute power intent (UPF/CPF), perform comprehensive EM/IR-drop analysis, and resolve dynamic and static voltage drop issues.

Physical Verification (Sign-off): Ensure tape-out readiness by achieving clean DRC, LVS, Antenna, and ERC checks.

Cross-Functional Collaboration: Partner closely with RTL, DFT, Custom Layout, and Architecture teams to iterate on floorplans, resolve congestion, and optimize Power, Performance, and Area (PPA) metrics.

Flow & Methodology: Develop, maintain, and optimize automation scripts and design flows to eliminate bottlenecks and improve team productivity.

Requirements

Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

Experience: 7–10+ years of hands‑on experience in Physical Design, with at least 2+ years acting as a technical lead or manager.

Technology Nodes: Proven track record of successful tape-outs in advanced FinFET/GAA technology nodes (e.g., 7nm, 5nm, 3nm).

EDA Tool Expertise: Deep proficiency in industry-standard tools:

Place & Route: Synopsys ICC2 / Fusion Compiler OR Cadence Innovus.

Sign-off Timing: Synopsys PrimeTime OR Cadence Tempus.

Physical Verification: Siemens Calibre, Synopsys ICV, OR Cadence Pegasus.

Power Analysis: RedHawk OR Voltus.

Scripting & Automation: Strong programming/scripting skills in TCL, Python, Perl, and Make.

Soft Skills: Excellent problem-solving, debugging, and communication skills with the ability to articulate complex technical issues to cross‑functional stakeholders.

Preferred Qualifications

Experience with high-frequency CPU/GPU core implementations.

Familiarity with advanced packaging methodologies (e.g., 2.5D, 3D‑IC, Chiplets).

Knowledge of machine learning (ML) optimization features within modern EDA tool suites.