Physical Design Manager

Mulya Technologies; Bengaluru; Hybrid; INR 4,000,000 - 6,000,000; Full time

Job summary

Mulya Technologies is seeking an experienced PD Manager to lead and scale Physical Design and CAD teams across locations. You will own end-to-end ASIC/SoC physical implementation including floorplanning, placement, CTS, routing, and tapeout.

The role requires strong expertise in timing closure, signal integrity, low-power verification, DRC/LVS, and collaboration with Architecture, RTL, DFT, Analog/Mixed-Signal, packaging, and program management teams.

Qualifications

• 12-20 years of experience in ASIC/SoC Physical Design & Timing Signoff.

Responsibilities

• Lead and scale high-performing Physical Design and CAD teams across multiple locations.
• Own end-to-end ASIC/SoC physical implementation including floorplanning, placement, CTS, routing, optimization, and tapeout.
• Drive timing closure, signal integrity, IR drop/EM analysis, DRC/LVS, and low-power verification signoff.
• Collaborate with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams.
• Drive methodology improvements, EDA tool optimization, automation, advanced packaging/chiplet flows, and AI-driven design initiatives.

Skills

Physical Design

Timing Signoff

People Management

ASIC/SoC

DVFS & Power Management

Low-Power Design

STA

DFT

Education

B.Tech / M.Tech in Electronics or Electrical Engineering

Tools

Synopsys Suite

Cadence Suite

Job description

We are a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships.

We are a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services.

We have an urgent open position for "PD Manager" and would appreciate your support in sourcing suitable candidates on priority. Below is the detailed JD for your reference.

• Experience: 12-20 Years
• Work Model: Hybrid (Work from Office)
• Education: B.Tech / M.Tech in Electronics, Electrical Engineering, or related disciplines

Key Responsibilities

• Lead and scale high-performing Physical Design and CAD teams across multiple locations.
• Own end-to-end ASIC/SoC physical implementation including floorplanning, placement, CTS, routing, optimization, and tapeout.
• Drive timing closure, signal integrity, IR drop/EM analysis, DRC/LVS, and low-power verification signoff.
• Collaborate closely with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams.
• Drive methodology improvements, EDA tool optimization, automation, advanced packaging/chiplet flows, and AI-driven design initiatives.

Required Skills

• 12-20 years of experience in ASIC/SoC Physical Design and Timing Signoff.
• Prior People Management Experience is mandatory.
• Minimum 2+ years of experience in a senior management or director-level role.
• Strong hands-on expertise in advanced technology nodes.
• Extensive experience with Synopsys and/or Cadence tool suites.
• Proven experience in full-chip implementation and successful tapeouts.
• Strong understanding of STA, signal integrity, low-power design, UPF/CPF, DRC/LVS, and physical methodologies.
• Deep knowledge of DVFS, power gating, multi-voltage architectures, and high-speed interfaces.

Preferred Skills

• Experience with advanced packaging and chiplet-based architectures.
• Strong leadership, stakeholder management, and team-building capabilities.