Sr. Lead Physical Verification

L&T Semiconductor Technologies; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

L&T Semiconductor Technologies in Bengaluru is seeking a senior-level Physical Verification Engineer to own sign-off flows for SoC/IPs and blocks. You will work hands-on on LVS, ERC, DFM, ESD, and Tapeout issues, driving validation methodologies and execution across projects.

The role requires strong debugging of LVS at chip level, experience with advanced nodes, and collaboration with design and sign-off teams. A bachelor's or master's in engineering is required.

Qualifications

• Bachelor's or Master's degree in Computer/Electronics/Electrical Engineering
• Hands-on expertise in LVS, ERC, PERC, DFM, OPC, and Tape-Out processes
• Experience on advanced nodes (5nm/7nm/12nm/14nm/16nm/22nm) at major foundries
• Strong debugging and problem-solving skills for sign-off issues
• Ability to develop and maintain sign-off methodologies and flows

Responsibilities

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out) of SoC/full-chip and block level
• Own physical verification and sign-off flows, methodologies and execution
• Experience in debugging LVS issues at chip level with complex analog-mixed signal IPs
• Develop sign-off methodology/flow and support a larger team
• Collaborate with design teams to ensure robust verification and sign-off

Skills

Physical verification

LVS

ERC

PERC

DFM

OPC

Tape-out process

Debugging LVS issues

Sign-off methodologies

Analog-Mixed-Signal awareness

Education

Bachelor's or Master's in Computer/Electronics/Electrical Engineering

Job description

This is senior-level position for physical verification who will work on SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/IP/Blocks.

Key Responsibilities

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level
• Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
• Experience in developing sign-off methodology/flow to and supporting a larger team
• Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
• Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
• Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
• Experience with ERC rules, PERC rules, ESD rules has an added advantage
• Strong communication skills, problem solving and analytical skills

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering