Senior Physical Design Engineer

SpeedMart; Chennai District; On-site; INR 3,000,000 - 5,200,000; Full time

Job summary

SpeedMart is seeking a seasoned Full-Chip Physical Verification Lead in Chennai, India. The role demands 8+ years of PV expertise, including PV signoff, DRC/LVS/ERC, and Flip-Chip experience, with strong PNR flow knowledge.

You will drive PV closure, mentor juniors, and coordinate with Physical Design, PNR, DFT, RTL, and circuit teams to ensure timely tape-out and signoff deliverables.

Qualifications

• 8+ years as Physical Verification Engineer required.
• Full-Chip PV and PV Signoff experience mandatory.
• Hands-on DRC/LVS/ERC and Antenna checks with PV closure.

Responsibilities

• Own and drive full-chip PV activities and signoff.
• Debug DRC/LVS/antenna violations and provide closure.
• Mentor engineers and drive PV timelines with cross-functional teams.
• Support tape-out activities and PV discussions with clients.

Skills

Physical Verification

PV Signoff

DRC Checks

LVS Checks

ERC Checks

Antenna Analysis

Flip-Chip Experience

PNR Tools

Physical Design

Place & Route

PV/PNR Tools

Tape-out Signoff

Team Mentoring

Education

Bachelor’s / Master’s in Electronics

Electrical/VLSI/Microelectronics

Tools

Siemens Calibre

Synopsys ICV/ICVWB

PVS

Cadence Innovus

ICC/ICC2

Fusion Compiler

Job description

Our client is a leading global provider of technology driven talent and Tech solutions, delivering technology-driven staffing, business services and managed workforce diverse industries. The organization specializes in helping enterprises build agile, scalable, and future-ready solutions through AI-enabled talent acquisition, workforce management, and digital HR solutions. With a strong international presence, it supports organizations in optimizing workforce productivity, improving operational efficiency, and accelerating business growth.

The organization serves diverse sectors including BFSI, Retail, Telecommunications, Manufacturing, Information Technology, Global Capability Centres (GCCs), Healthcare, and other key industries, helping clients accelerate growth, improve operational efficiency, and drive business transformation.

Job Profile : Full-Chip Physical Verification Lead

Work Mode: Work from office (WFO)

Preferred experience: 8+ years

The Role:

We are looking for experienced Full-Chip Physical Verification Leads with strong hands‑on experience in Physical Verification, PV signoff, DRC, LVS, ERC, Antenna and complex subsystem/full‑chip PV closure. The ideal candidate should have strong knowledge of Physical Design and PNR flow, along with hands‑on experience using PNR tools for route fixes and PV closure. Flip‑chip experience is mandatory for this role.

Responsibilities:

• Own and drive full‑chip Physical Verification (PV) activities and signoff.
• Handle complex subsystem PV closure where full‑chip experience is not available.
• Perform and debug DRC, LVS, ERC and Antenna violations.
• Drive PV violation analysis, debugging and closure within project timelines.
• Work closely with Physical Design, PNR, DFT, RTL, circuit and other cross‑functional teams.
• Understand the PNR / Place & Route flow and identify physical implementation issues impacting PV.
• Use PNR tools for route fixes and support physical design teams in resolving routing‑related violations.
• Analyze and resolve DRC/LVS/antenna and other physical verification issues.
• Support full‑chip and subsystem‑level signoff and tape‑out activities.
• Review PV reports, identify root causes and drive corrective actions.
• Support technical discussions with internal teams and clients.
• Mentor junior engineers and provide technical guidance on PV closure activities.
• Ensure quality, accuracy and timely completion of PV signoff deliverables.

Must - Have Qualifications:

• Minimum 8 years of experience as a Physical Verification Engineer.
• Experience in Full‑Chip Physical Verification (PV) and PV Signoff
• Experience in Complex Subsystem PV Closure
• Hands‑on experience in DRC, LVS, ERC and Antenna checks and closure
• Mandatory Flip‑Chip experience
• Good understanding of PNR / Place & Route flow
• Hands‑on experience with PNR tools for route fixes
• Experience in Physical Design, Placement and Routing
• Experience in PV violation analysis, debugging and closure
• Experience in Tape‑out / Signoff activities
• Experience with PV/PNR tools such as Siemens Calibre, Synopsys ICV/ICVWB, PVS, Cadence Innovus, ICC/ICC2, Fusion Compiler or equivalent
• Experience working with Physical Design, PNR, DFT, RTL and Circuit Design teams
• Experience with Timing Closure and physical implementation fixes
• Experience with advanced technology nodes and complex semiconductor designs

Preferred Qualifications:

• Bachelor’s / Master’s degree in Electronics, Electrical, VLSI, Microelectronics or related engineering discipline.
• Experience in advanced technology nodes.
• Experience with multiple PV/PNR tools and ability to adapt to different tool flows.
• Experience in team leadership, mentoring and technical ownership.