Senior Physical Design Engineer

ACL Digital; Pune District; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading technology firm in Pune is seeking an experienced Physical Verification Engineer to join their VLSI team. The candidate will be responsible for ensuring layout correctness and manufacturability before tape-out, performing physical verification checks, and developing automation scripts. Strong expertise in DRC, LVS, ERC, and experience with Physical Verification tools like IC Validator or Cadence PVS is essential. The role also requires mentoring junior engineers and supporting project planning, making it an exciting opportunity for career growth.

Qualifications

• Strong experience in Physical Verification tools is required.
• Good understanding of ASIC Physical Design flow needed.
• Experience in advanced technology nodes (16nm / 7nm / 5nm preferred).

Responsibilities

• Perform Physical Verification sign-off checks including DRC, LVS,/ERC.
• Debug and resolve DRC/LVS violations with teams.
• Develop automation scripts for verification flows.
• Mentor junior engineers and support project planning.

Skills

Physical Verification tools

DRC, LVS, ERC expertise

Automation scripting

Tools

IC Validator (ICV)

Cadence PVS

Job description

We are looking for an experienced Physical Verification Engineer to join our VLSI team. The candidate will be responsible for full-chip and block-level physical verification, ensuring layout correctness and manufacturability before tape-out. The role requires strong expertise in DRC, LVS, ERC, and sign-off flows along with collaboration across Physical Design, Layout, and CAD teams.

Key Responsibilities:

• Perform Physical Verification sign-off checks including:
• DRC (Design Rule Check)
• LVS (Layout vs Schematic)
• ERC (Electrical Rule Check)
• Density / DFM checks
• Debug and resolve DRC/LVS violations with layout and design teams.
• Handle block-level and full-chip physical verification.
• Work with foundry rule decks and ensure compliance.
• Perform parasitic extraction (PEX) and support timing/SI teams.
• Support tape-out activities and sign-off closure.
• Develop automation scripts for verification flows.
• Mentor junior engineers and support project planning.

Required Skills:

• Strong experience in Physical Verification tools:
• IC Validator (ICV) or Cadence PVS
• Good understanding of:
• ASIC Physical Design flow
• CMOS layout concepts
• GDSII / OASIS formats
• Experience in advanced technology nodes (16nm / 7nm / 5nm preferred).