Physical Verification Engineer

Erbity; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Erbity is seeking a Physical Verification Engineer to lead full-chip and block-level PV signoff across advanced nodes. You will debug DRC/LVS/ERC/ANT issues, run PV flows with Calibre, and collaborate with Physical Design, Layout, and Foundry teams to ensure clean tapeouts.

We expect 5+ years in PV, strong scripting in Tcl/Perl/Python, and hands-on Calibre experience. Knowledge of 16nm/7nm/5nm nodes and CMOS manufacturing will be highly valued.

Qualifications

• 5+ years of experience in Physical Verification.
• Expertise in DRC, LVS, ERC, ANT, Density, DFM and Signoff.
• Hands-on experience with Mentor Calibre (DRC/LVS/PERC) or equivalent PV tools.
• Understanding of IC layout, CMOS process and semiconductor manufacturing.
• Experience with advanced nodes (16nm/7nm/5nm or below).
• Scripting with Tcl, Perl or Python.
• Strong debugging, analytical and problem-solving skills.

Responsibilities

• Perform block and full-chip Physical Verification (PV) signoff.
• Debug and resolve DRC, LVS, ERC, ANT, Density, and DFM violations.
• Execute PV flows using Calibre or equivalent EDA tools.
• Collaborate with Physical Design, Layout, and Foundry teams to achieve clean tapeout.
• Develop and maintain automation scripts using Tcl, Perl, or Python.
• Support multiple technology nodes including 28nm, 16nm, 7nm, 5nm, or below.

Skills

Physical Verification

DRC/LVS/ERC

Calibre/ PV tools

Scripting (Tcl/Perl/Python)

IC layout / CMOS process

Advanced nodes (16/7/5nm)

Debugging/Analytical

Education

BE/B.Tech/M.Tech in Electronics/VLSI

Tools

Calibre

Job description

Role Overview

We are looking for a Physical Verification Engineer with strong expertise in full-chip and block-level physical verification for advanced technology nodes. The ideal candidate should have hands-on experience in DRC, LVS, ERC, and Physical Verification signoff using industry-standard EDA tools while working closely with Physical Design, Layout, and Foundry teams.

• Perform block and full-chip Physical Verification (PV) signoff.


• Debug and resolve DRC, LVS, ERC, ANT, Density, and DFM violations.


• Execute PV flows using Calibre or equivalent EDA tools.


• Collaborate with Physical Design, Layout, and Foundry teams to achieve clean tapeout.


• Develop and maintain automation scripts using Tcl, Perl, or Python.


• Support multiple technology nodes including 28nm, 16nm, 7nm, 5nm, or below.

Requirements

• 5+ years of experience in Physical Verification.


• Strong expertise in DRC, LVS, ERC, ANT, Density, DFM, and Signoff.


• Hands-on experience with Mentor Calibre (DRC/LVS/PERC) or equivalent PV tools.


• Good understanding of IC layout, CMOS process, and semiconductor manufacturing.


• Experience with advanced technology nodes (16nm/7nm/5nm or below).


• Scripting knowledge in Tcl, Perl, or Python.


• Strong debugging, analytical, and problem-solving skills.

• Preferred Skills

• Experience with PERC, ESD/Latch-up verification.


• Exposure to FinFET technology and foundry signoff flows (TSMC/Samsung/Intel/GlobalFoundries).


• Knowledge of Physical Design flow and tapeout methodology.

Education: BE/B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related discipline.