Senior Physical Design Engineer

BITSILICA; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

BITSILICA in Bengaluru is seeking a Senior Physical Design Engineer to drive end-to-end implementation of complex SoCs at advanced nodes, collaborating with synthesis, STA and DFT teams to meet PPA targets.

The role requires hands-on experience with netlist-to-GDSII flow, STA timing, DRC/LVS/ER, IR drop and EM analyses, and low-power techniques. You will interface with RTL and DFT teams to optimize physical constraints.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Experience with sNetlist-to-GDSII flow including Floorplanning, Placement, CTS and Routing.
• Experience with Static Timing Analysis (STA) and timing closure across corners and modes.
• Knowledge of UPF/CPF low-power methodologies.
• Familiarity with DRC/LVS/ER and antenna checks.

Responsibilities

• Execute the complete physical design flow from netlist to GDSII.
• Perform timing closure across corners and modes (setup, hold, recovery, removal).
• Own and resolve DRC, LVS, ERC and Antenna violations.
• Conduct IR drop and EM analyses for robust power delivery.
• Collaborate with RTL and DFT teams to resolve constraints and optimize design.

Skills

Scripting (Tcl/Perl/Python)

Multi-voltage domains

Congestion management

Hierarchical design

Education

Bachelor’s or Master’s degree in Electrical/Electronics Engineering

Tools

Innovus (Cadence)

ICC2 (Synopsys)

Calibre

Assura

Job description

As a Senior Physical Design Engineer, you will be responsible for the end-to-end implementation of complex SoCs at advanced process nodes (e.g., 7nm, 5nm, and below). You will work closely with the synthesis, STA, and DFT teams to deliver high-quality GDSII, ensuring all PPA (Power, Performance, Area) targets are met.

Responsibilitie

• sNetlist-to-GDSII Flow: Execute the complete physical design flow, including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing
• .Timing Closure: Perform Static Timing Analysis (STA) and timing closure across all corners and modes (setup, hold, recovery, removal)
• .Physical Verification: Own and resolve DRC, LVS, ERC, and Antenna violations using industry-standard tools
• .Power Analysis: Conduct IR drop analysis (Static and Dynamic) and EM (Electromigration) analysis to ensure robust power delivery
• .Optimization: Implement area reduction techniques and low-power design methodologies (UPF/CPF)
• .Collaboration: Interface with the RTL and DFT teams to resolve design hurdles and provide feedback on physical constraints

Qualificatio

• nsBachelor’s or Master’s degree in Electrical/Electronics Engineering or a related fiel

d.Required Ski

• llsEDA Tools: Proficiency in industry-leading tools such as Innovus (Cadence) or ICC2 (Synopsy
• s).Verification Tools: Hands-on experience with Calibre, Assura, or I
• CV.Methodology: Strong understanding of hierarchical design, multi-voltage domains, and congestion manageme
• nt.Nodes: Experience working on advanced process nodes (7nm/5nm/3n
• m).Scripting: Ability to automate tasks using Tcl, Perl, or Pyth

on.Preferred Sk

• illsStrong analytical and problem-solving ski
• lls.Excellent communication skills for cross-functional team coordinat