PV Engineer

Incise Infotech Pvt. Ltd.; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Incise Infotech Pvt. Ltd. in Bengaluru is looking for a skilled professional in physical verification for SoC and block-level designs. The role involves developing sign-off methodologies and addressing LVS issues in complex analog-mixed signal designs.

The ideal candidate should have experience in Tape Out processes and work with 5nm to 22nm nodes, along with strong analytical and communication skills.

Qualifications

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level.
• Preferably worked on 5nm to 22nm nodes.
• Strong communication, problem-solving, and analytical skills.

Responsibilities

• Develop sign-off methodology/flow to support a larger team.
• Debug LVS issues at chip-level with complex analog-mixed signal designs.
• Perform physical verification of I/O Ring, corner cells, seal ring, RDL routing, and bumps.

Skills

Physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process)

Debugging LVS issues

Low-power implementation design

Job description

LVS ERC/PERC DFM OPC Tape Out process Physical Verification calibre

Job Description

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level
• Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
• Experience in developing sign-off methodology/flow to and supporting a larger team
• Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
• Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
• Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
• Experience with ERC rules, PERC rules, ESD rules has an added advantage
• Strong communication skills, problem solving and analytical skills