Physical Verification Engineer (Staff / Sr. Staff)

Velaura; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Velaura invites applications for a Staff/Sr. Staff Physical Verification Engineer to own block-level and full-chip PV signoff for next‑gen AI and HPC silicon in Bengaluru, India.

You will drive DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability checks, and perform root-cause fixes directly in Cadence Innovus and/or Synopsys Fusion Compiler, collaborating with Physical Design, STA, Power Integrity, and CAD teams to ensure first‑time‑right silicon.

Qualifications

• Deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification.

Responsibilities

• Own block-level and full-chip physical verification signoff, including DRC, LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex ASIC/SoC designs.
• Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking, and convergence to zero or signoff-acceptable violations.
• Execute and debug physical verification using industry-standard tools such as Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity, device-recognition, hierarchy, and advanced-node rule issues.
• Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion Compiler implementation databases and drive physical fixes through iterative verification to closure.

Skills

DRC

LVS

ERC

PERC

antenna

ESD/EOS

reliability verification

Cadence Innovus

Synopsys Fusion Compiler

Calibre

IC Validator (ICV)

Tools

Cadence Innovus

Synopsys Fusion Compiler

Calibre

IC Validator (ICV)

Job description

Role Overview

As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. You will drive physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies.

This is a highly hands-on technical role requiring deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification, along with the ability to identify root causes and implement physical fixes directly in Cadence Innovus and/or Synopsys Fusion Compiler.

You will work closely with Physical Design, Analog/Mixed-Signal, STA, Power Integrity, Reliability, I/O, and CAD teams to drive signoff convergence, establish robust PV methodologies, and achieve first-time-right silicon.

Responsibilities

• Own block-level and full-chip physical verification signoff, including DRC, LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex ASIC/SoC designs.
• Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking, and convergence to zero or signoff-acceptable violations.
• Execute and debug physical verification using industry-standard tools such as Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity, device-recognition, hierarchy, and advanced-node rule issues.
• Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion Compiler implementation databases and drive physical fixes through iterative verification to closure.