Sr. Lead Physical Verification

L&T Semiconductor Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

L&T Semiconductor Technologies is seeking a senior Physical Verification engineer to own LVS, ERC/PERC, DFM, OPC sign-off flows for SoC and blocks. This hands-on role focuses on solving critical design and execution issues to ensure robust sign-off and successful tapeout across advanced nodes.

The candidate will develop sign-off methodologies, debug LVS at chip level for complex analog/mixed-signal IPs, and contribute to power-aware verification and flow improvements.

Qualifications

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/full-chip or block level.
• Experience with 5nm/7nm/12nm/14nm/16nm/22nm nodes at major foundries.
• Ability to develop sign-off methodologies/flows and support a larger team.
• Experience debugging LVS issues at chip level with complex analog/mixed signal IPs.
• Experience with low-power implementation (level-shifters, isolation cells, power domains, islands, substrate isolation).
• Proficient in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and full-chip components.
• Knowledge of ERC rules, PERC rules, ESD rules is a plus.
• Strong communication, problem solving, and analytical skills.

Responsibilities

• Own physical verification and sign-off flows, methodologies and execution for SoC/IP/Blocks.
• Prepare and execute sign-off strategies for complex designs across nodes.
• Debug LVS issues at chip level, including analog/mixed-signal IPs, with cross-functional teams.
• Develop low-power verification techniques and verify power domains, isolation cells and related constraints.
• Verify I/O Ring, corner cells, seal ring, RDL routing and other full-chip components across blocks.

Skills

LVS

ERC/PERC

DFM

OPC

Tapeout

Sign-off flows

Debugging LVS

Low-power design

Education

Bachelor's or Master's degree in Computer/Electronics/Electrical Engineering

Job description

This is senior-level position for physical verification who will work on SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/IP/Blocks.

Key Responsibilities

• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level
• Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
• Experience in developing sign-off methodology/flow to and supporting a larger team
• Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
• Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
• Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
• Experience with ERC rules, PERC rules, ESD rules has an added advantage
• Strong communication skills, problem solving and analytical skills

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering