Physical Design Lead (Full Chip)

7Rays Semiconductors; Delhi; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

7Rays Semiconductors in Noida is seeking a Senior Physical Design Engineer to lead complex SoC floorplanning and sign-off activities. You will drive physical verification readiness and collaborate with routing and analog teams to ensure design intent is met.

The ideal candidate has 7–12+ years in physical design, strong Innovus experience, IO ring strategies, and deep scripting skills (TCL/Perl/Makefile). You will proactively resolve tool, flow, and design setup issues for a large team.

Qualifications

• 7+ years experience in Physical Design.
• Expertise in Floorplanning for SoC using Innovus.
• Knowledge and implementation strategies to create an IO ring per design spec.
• Deep knowledge on ESD, latch-up for foundry requirements.
• Hierarchical design implementation knowledge including partitions/HMs/tiles push down to each core/tile.
• PG creation and push down methodologies knowledge.
• Knowledge on Analog components and their placement requirements.
• RDL knowledge and packaging for SoC floorplan.
• PV cleanup on floorplan and sign-off including ESD and foundry/Analog requirements.
• Deep scripting knowledge in TCL/Perl/Makefile; experience developing complex P&R algorithms.
• Familiar with sign-off issues (metal-fill, spare-cells, DFM rules) for latest process techs.

Responsibilities

• Design floorplan for SoC ensuring timing and area targets.
• PV sign-off readiness and collaboration with routing and analog teams.
• Develop and maintain P&R flows and scripts to automate check processes.

Skills

Physical Design

Floorplanning

Innovus

TCL/Perl scripting

Algorithm development

Interpersonal skills

Education

Bachelor's in EE/EC/CS

Tools

Innovus

Job description

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job: Senior Physical Design Engineer

Experience: 7–12+ years

Location: Noida

• 7+ years experience in Physical Design
• Extensive expertise in Floorplanning for SoC using Innovus
• Must have a knowledge and implementation strategies to create an IO ring in accordance design specification
• Have a deep knowledge on ESD, latch-up etc for foundary requirements and placement strategies
• Should have a higherarchial design implementation knowledge which include partitions/HMs/tiles push down to each core/tile
• PG creation and push down methodologies knowledge and implementation
• Should have a knowledge on Analog components and their requirements in placements according to design specifications
• RDL knowledge and working with packaging is a must for SoC floorplan designer
• PV clean-up on floorplan and self derive in all the sign-off including Physical Verification, ESD and foundry/Analog requirements
• Deep scripting knowledge is essential
• Should be capable of providing solutions to flow, tool, design setup elated issues proactively at large team level
• Strong TCL/Perl/Makefile scripting knowledge as well as experience developing complex algorithms, managing, and regressing P&R flows.
• Familiar with sign-off issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies
• Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills
• Bachelors Degree in Electrical, Electronics or Computer Engineering