Sr. Lead Physical Design - Power/IR/EM Engineering

Larsen & Toubro; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Larsen & Toubro in Bengaluru, India is seeking a Sr Lead Physical Design to helm full-chip level PDN planning for peak current and voltage response at the SOC level.

The role requires leading EMIR signoff, dynamic and static IR analysis, and close collaboration with system, PMIC and silicon package teams to ensure robust grid behavior. A strong scripting and data-analysis background with EDA tool experience is essential.

Qualifications

• Bachelor's or Master's degree in Computer/Electronics/Electrical Engineering.
• 10+ years of relevant experience in physical design and power integrity.
• Experience with EMIR signoff and IC-level PDN modeling desirable.

Responsibilities

• Develop and run EMIR signoff flow at SOC level.
• Close EMIR based on dynamic and static IR drop analyses.
• Provide feedback on grid robustness to the SOC floorplan team.
• Collaborate with system, PMIC and silicon package teams to model voltage response of the PDN.
• Model power delivery networks including on-die power gating and in-rush profiles.
• Model current profiles and peak current demands of various IPs.
• Demonstrate problem solving, scripting, data analysis, and use of EDA tools.
• Thrive in teamwork, flexibility and dynamic environments.

Skills

Problem solving

Scripting

Data analysis

EDA tools

Education

Bachelor's or Master's in Computer/Electronics/Electrical Engineering

Tools

EDA tools

Job description

Relevant Experience 10-18 Years

Role: Sr Lead Physical Design

This position is for senior level engineer Full chip level Power Distribution Network Design. He Shall be leading instrumental in power grid planning on SoC level for peak current requirements & to have Dynamic & Static IR drop assessment & closure.

Key Responsibilities

• Ability to Develop & run EMIR Signoff flow at SOC
• Ability to Close EMIR based on Dynamic (vectored and vectorless) & Static IR
• Can provide Feedback on Grid Robustness to SOC floorplan team
• Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.
• Model of the power delivery networks, including on-die power gating and in-rush current profiles.
• Model of the current profiles and peak current demands of various IPs
• Strong Skills in problem solving, scripting, data analysis and experience with EDA tools.
• Teamwork / flexibility / ability to thrive in a dynamic environment are very important

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

electronics/Electrical Engineering