Senior Staff Engineer – Physical Design (EMIR)

LeadSOC Technologies Pvt Ltd; Bengaluru; Híbrido; INR 4.000.000 - 7.000.000; Jornada completa

Descripción de la vacante

LeadSOC Technologies Pvt Ltd in Bengaluru is seeking a Senior Staff Engineer with deep expertise in ASIC/SoC Physical Design, EMIR and IR drop analysis to own EMIR sign-off and PDN optimization across advanced nodes.

You will drive end-to-end physical design activities, from floorplanning to routing, analyze and debug EMIR violations, and collaborate with RTL, synthesis, timing and PD teams to ensure reliable power integrity.

Formación

• 10–15 years of hands-on ASIC/SoC Physical Design experience.
• Strong expertise in EMIR analysis, debugging, optimization, and sign-off.
• Experience with static and dynamic IR drop, signal EM, power-grid EM, and power integrity analysis.
• Proficiency with industry-standard PD tools such as Cadence Voltus, Ansys RedHawk-SC, or equivalent.

Responsabilidades

• Drive end-to-end physical design activities (floorplanning, placement, CTS, routing, sign-off).
• Own EMIR analysis and sign-off, including static/dynamic IR drop and power-grid EM analysis.
• Analyze and debug EMIR violations; perform root-cause analysis and implement fixes.
• Optimize PDN, power straps, vias, and power-grid connectivity for reliability and voltage drop targets.
• Perform power integrity analysis across modes, corners and activity scenarios.
• Collaborate with RTL, synthesis, timing, and PD teams to resolve power/timing issues.
• Drive timing, congestion, power, and area optimization while maintaining EMIR constraints.
• Support sign-off closure through ECOs and tool correlation; develop EMIR automation scripts.

Conocimientos

EMIR analysis

IR drop analysis

Physical Design

Floorplanning

Placement

CTS

Routing

Power integrity

Scripting (Tcl)

Python/Perl scripting

Educación

BE/BTech/M.E/M.Tech in Electrical/Electronics

Herramientas

Cadence Voltus

Ansys RedHawk-SC

Descripción del empleo

Senior Staff Engineer – Physical Design (EMIR)

Experience: 10–15 Years

Role Overview

We are looking for a technically strong Senior Staff Engineer with deep expertise in Physical Design and Electromigration (EM) and IR Drop (IR) analysis for complex ASIC/SoC designs. The role focuses on power integrity, EMIR sign-off, physical implementation optimization, and closure across advanced technology nodes.

Key Responsibilities

• Drive end-to-end physical design activities, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical sign-off.
• Own EMIR analysis and sign-off, including static and dynamic IR drop, signal EM, and power-grid EM analysis.
• Analyze and debug EMIR violations; drive root-cause analysis and implement corrective actions.
• Optimize power distribution networks (PDN), power straps, via structures, and power-grid connectivity to meet reliability and voltage-drop requirements.
• Perform power integrity analysis across multiple operating modes, corners, and activity scenarios.
• Collaborate with RTL, synthesis, timing, and physical design teams to resolve power integrity and timing-related issues.
• Drive timing, congestion, power, and area optimization while maintaining EMIR and reliability constraints.
• Support sign-off closure through iterative analysis, ECO implementation, and correlation between implementation and sign-off tools.
• Develop automation scripts and methodologies to improve EMIR analysis efficiency and sign-off quality.

Required Technical Skills

• 10–15 years of hands-on experience in ASIC/SoC Physical Design.
• Strong expertise in EMIR analysis, debugging, optimization, and sign-off.
• Experience with static and dynamic IR drop, signal EM, power-grid EM, and power integrity analysis.
• Proficiency in industry-standard tools such as Cadence Voltus, Ansys RedHawk-SC, or equivalent.
• Strong understanding of power delivery networks, power-grid design, current density, voltage drop, and electromigration reliability.
• Hands-on experience with floorplanning, placement, CTS, routing, and physical sign-off.
• Strong understanding of STA, timing closure, power optimization, and physical implementation trade-offs.
• Experience with advanced technology nodes, multi-corner analysis, and sign-off methodologies.
• Proficiency in Tcl scripting; Python or Perl scripting is an advantage.

Preferred Qualifications

• Experience with high-performance CPU, GPU, networking, or complex SoC designs.
• Exposure to advanced-node power integrity challenges and reliability sign-off.
• Experience with EMIR methodology development, automation, and cross-functional technical leadership.

Education:

B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline.