Senior Physical Design Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru, India is seeking a Senior Physical Design Engineer with strong hands-on EM/IR analysis and sign-off for complex ASIC/SoC designs.

You will work with cross-functional teams on EM/IR analysis, PG optimization, power integrity, and sign-off closure, using Cadence Voltus and Ansys RedHawk, and contribute to tape-out readiness.

Qualifications

• 5-10 years of ASIC/SoC Physical Design experience.
• Strong hands-on experience in EM/IR analysis and closure.
• Experience with Cadence Voltus, Ansys RedHawk or equivalent.
• Good understanding of power distribution networks, IR drop, electromigration and power integrity.
• Strong knowledge of physical design, P&R and sign-off flows.
• Understanding of STA, MMMC and advanced-node design challenges.
• Strong debugging and scripting skills.
• Experience with full-chip/block-level EM/IR sign-off preferred.

Responsibilities

• Perform EM/IR analysis, debugging and sign-off for block and full-chip designs.
• Analyze static/dynamic IR drop, electromigration and power integrity issues.
• Drive EM/IR closure through power-grid optimization, PG strengthening and physical ECOs.
• Work with Physical Design, STA, RTL, DFT and Power teams to resolve PI issues.
• Perform vector-based and vectorless EM/IR analysis and correlate with design activity.
• Debug IR drop hotspots, EM violations and power-grid reliability issues.
• Support power planning, PG mesh/stripe optimization and PI sign-off.
• Analyze impact of placement, routing, clocking and PD on EM/IR.
• Automate analysis and reporting using Tcl/Python/Perl.
• Support tape-out and sign-off closure for advanced-node designs.

Skills

5-10 years

EM/IR analysis

Physical Design

P&R and sign-off flows

STA

MMM C

Scripting

Full-chip EM/IR sign-off

Debugging

Power integrity

Power-grid optimization

EM/IR closure

Vector-based EM/IR analysis

Vectorless EM/IR analysis

Tcl/Python/Perl

Tools

Cadence Voltus

Ansys RedHawk

Job description

We are looking for a Senior Physical Design Engineer with strong hands-on expertise in EM/IR analysis and physical design sign-off for complex ASIC/SoC designs.

Key Responsibilities

• Perform EM/IR analysis, debugging and sign-off for block and full-chip designs.
• Analyze static/dynamic IR drop, electromigration and power integrity issues.
• Drive EM/IR closure through power-grid optimization, PG strengthening and physical ECOs.
• Work closely with Physical Design, STA, RTL, DFT and Power teams to resolve power integrity issues.
• Perform vector-based and vectorless EM/IR analysis and correlate results with design activity.
• Debug IR drop hotspots, EM violations and power-grid reliability issues.
• Support power planning, PG mesh/stripe optimization and power integrity sign-off.
• Analyze the impact of placement, routing, clocking and power distribution on EM/IR.
• Automate analysis and reporting using Tcl/Python/Perl.
• Support tape-out and sign-off closure for advanced-node designs.

Required Skills

• 5-10 years of ASIC/SoC Physical Design experience.
• Strong hands-on experience in EM/IR analysis and closure.
• Experience with Cadence Voltus, Ansys RedHawk or equivalent.
• Good understanding of power distribution networks, IR drop, electromigration and power integrity.
• Strong knowledge of physical design, P&R and sign-off flows.
• Understanding of STA, MMMC and advanced-node design challenges.
• Strong debugging and scripting skills.
• Experience with full-chip/block-level EM/IR sign-off preferred.