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L&T Semiconductor Technologies in Bengaluru, India seeks a senior level engineer to lead full chip level Power Distribution Network design. You will drive EMIR signoff at the SOC level, assess dynamic and static IR drops, and collaborate with PMIC and silicon package teams to model voltage responses of the power delivery network.
Candidate should hold a Bachelor's or Master's degree in Computer/Electronics/Electrical Engineering with strong scripting, data analysis, and EDA tool experience to
This position is for senior level engineer Full chip level Power Distribution Network Design. He Shall be leading instrumental in power grid planning on SoC level for peak current requirements & to have Dynamic & Static IR drop assessment & closure.
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering