Sr. Lead Physical Design - Power/IR/EM Engineering

L&T Semiconductor Technologies

Bengaluru

On-site

INR 1,800,000 - 3,000,000

Full time

3 days ago
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Job summary

L&T Semiconductor Technologies in Bengaluru, India seeks a senior level engineer to lead full chip level Power Distribution Network design. You will drive EMIR signoff at the SOC level, assess dynamic and static IR drops, and collaborate with PMIC and silicon package teams to model voltage responses of the power delivery network.

Candidate should hold a Bachelor's or Master's degree in Computer/Electronics/Electrical Engineering with strong scripting, data analysis, and EDA tool experience to

Qualifications

  • Experience with EMIR Signoff flow at SOC level.
  • Strong ability in IR drop analysis (dynamic & static).
  • Proficient in scripting, data analysis, and problem solving.
  • Experience with EDA tools; ability to adapt to new tools.

Responsibilities

  • Develop & run EMIR Signoff flow at SOC.
  • Close EMIR based on Dynamic and Static IR.
  • Provide feedback on grid robustness to SOC floorplan team.
  • Model voltage response of power delivery network with system/PMIC/silicon package teams.
  • Model PDN including on-die power gating and in-rush current profiles.
  • Model current profiles and peak current demands of various IPs.
  • Collaborate with team; strong teamwork and adaptability.

Job description

This position is for senior level engineer Full chip level Power Distribution Network Design. He Shall be leading instrumental in power grid planning on SoC level for peak current requirements & to have Dynamic & Static IR drop assessment & closure.

Key Responsibilities
  • Ability to Develop & run EMIR Signoff flow at SOC
  • Ability to Close EMIR based on Dynamic (vectored and vectorless) & Static IR
  • Can provide Feedback on Grid Robustness to SOC floorplan team
  • Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.
  • Model of the power delivery networks, including on-die power gating and in-rush current profiles.
  • Model of the current profiles and peak current demands of various IPs.
  • Strong Skills in problem solving, scripting, data analysis and experience with EDA tools.
  • Teamwork / flexibility / ability to thrive in a dynamic environment are very important
Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

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