EMIR / Power Integrity Engineer

Aion Silicon Ltd; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Aion Silicon Ltd is seeking an experienced EMIR / Power Integrity Engineer to join the SoC Physical Design team. You will lead PDN planning, perform PI/EMIR analysis, and drive signoff for advanced chip designs.

Responsibilities include EMIR verification, IR drop analysis, ECO implementation, and collaboration with design, CAD, and reliability teams to optimize power delivery and ensure signoff-quality results.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• 5+ years of ASIC/SoC EMIR experience.
• Knowledge of UPF and low-power design methodologies.
• Experience developing signoff methodologies and CAD automation flows.
• Understanding of package parasitics and power delivery architecture.
• Strong analytical, debugging, and communication skills.
• Strong understanding of:
• Power Delivery Networks (PDN)
• Electromigration (EM)
• Static and Dynamic IR Drop Analysis
• Power Integrity and Reliability Concepts
• Familiarity with Physical Design flow including Floorplanning, Placement, CTS, Routing, and Signoff.
• Experience with advanced technology nodes (7nm, 5nm, 3nm, or below).
• Strong scripting skills in Tcl, Python, Perl, or Shell.

Responsibilities

• Perform Power Integrity and EMIR analysis for complex SoC, subsystem, and IP designs.
• Develop, analyze, and optimize Power Delivery Networks (PDN) to meet performance, power, and reliability requirements.
• Execute Static IR Drop, Dynamic IR Drop, and Electromigration (EM) analysis throughout the design cycle.
• Define simulation methodologies, run setups, and signoff criteria for power integrity verification.
• Develop and enhance CAD-based EMIR analysis flows incorporating timing, package, and board-level abstractions.
• Identify, debug, and root-cause EM, Static IR, and Dynamic IR violations.
• Provide and implement ECO solutions to resolve power integrity violations, including power grid enhancements, strap optimization, cell spreading, decap insertion, power routing improvements, and layout modifications.
• Validate ECO effectiveness through iterative EMIR analysis and drive complete signoff closure.
• Collaborate closely with Physical Design, CAD, RTL, Package, and Reliability teams to achieve power integrity goals.
• Automate analysis, debugging, and reporting flows using Tcl, Python, Perl, or Shell scripting.
• Support advanced technology nodes and contribute to methodology development and continuous improvement.

Skills

Power Integrity

EMIR analysis

Debugging

Scripting

Communication

Education

Electrical/Electronics Engineering degree

Tools

Cadence Voltus

Ansys RedHawk/RedHawk-SC

Synopsys PrimeRail/PrimePower

Cadence Innovus

Synopsys ICC2

FC_SHELL

Job description

We are seeking a skilled EMIR / Power Integrity Engineer to join our SoC Physical Design team. The ideal candidate will be responsible for power delivery network (PDN) planning, power integrity analysis, EMIR verification, and signoff for advanced semiconductor designs. The role involves ensuring reliable power delivery across the chip through static and dynamic IR drop analysis, electromigration verification, power grid optimization, and ECO implementation to achieve signoff-quality designs.

Key Responsibilities

Perform Power Integrity and EMIR analysis for complex SoC, subsystem, and IP designs.

Develop, analyze, and optimize Power Delivery Networks (PDN) to meet performance, power, and reliability requirements.

Execute Static IR Drop, Dynamic IR Drop, and Electromigration (EM) analysis throughout the design cycle.

Define simulation methodologies, run setups, and signoff criteria for power integrity verification.

Develop and enhance CAD-based EMIR analysis flows incorporating timing, package, and board-level abstractions.

Identify, debug, and root-cause EM, Static IR, and Dynamic IR violations.

Provide and implement ECO solutions to resolve power integrity violations, including power grid enhancements, strap optimization, cell spreading, decap insertion, power routing improvements, and layout modifications.

Validate ECO effectiveness through iterative EMIR analysis and drive complete signoff closure.

Collaborate closely with Physical Design, CAD, RTL, Package, and Reliability teams to achieve power integrity goals.

Automate analysis, debugging, and reporting flows using Tcl, Python, Perl, or Shell scripting.

Support advanced technology nodes and contribute to methodology development and continuous improvement.

Required / Preferred Qualifications

Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.

5+ years of ASIC/SoC EMIR experience.

Knowledge of UPF and low-power design methodologies.

Experience developing signoff methodologies and CAD automation flows.

Understanding of package parasitics and power delivery architecture.

Strong analytical, debugging, and communication skills.

Strong understanding of:

Power Delivery Networks (PDN)

Electromigration (EM)

Static and Dynamic IR Drop Analysis

Power Integrity and Reliability Concepts

Familiarity with Physical Design flow including Floorplanning, Placement, CTS, Routing, and Signoff.

Experience with advanced technology nodes (7nm, 5nm, 3nm, or below).

Strong scripting skills in Tcl, Python, Perl, or Shell.

Tools Required

Cadence Voltus, Ansys RedHawk/RedHawk-SC, Synopsys PrimeRail/PrimePower for EMIR, Static/Dynamic IR Drop analysis, Power Integrity verification, and signoff.

Cadence Innovus / Synopsys ICC2 / FC_SHELL for power grid implementation, ECO execution, decap insertion, and EMIR closure.

Tcl, Python, Perl, and Shell Scripting for flow automation, methodology development, debugging, and reporting.