Senior EMIR Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; Vor Ort; INR 1.200.000 - 1.600.000; Vollzeit

Zusammenfassung

LeadSOC Technologies Pvt Ltd in Bengaluru seeks an EMIR Engineer to drive power integrity, IR drop, and electromigration analysis for advanced SoC designs. The role requires mentoring a team and shaping EMIR sign-off flows.

The candidate will lead cross-functional collaboration across RTL, PD, verification, and packaging to ensure robust power delivery and design convergence.

Qualifikationen

• 3–6 years of EMIR engineering experience.
• Strong expertise in EMIR sign-off methodology.
• Experience with PDN architecture planning and power integrity.

Aufgaben

• Lead IR drop, electromigration, and power integrity analysis across blocks and full-chip designs.
• Define, implement, and optimize EMIR sign-off flows using industry tools such as Redhawk, Voltus, and Totem.
• Drive PDN architecture planning and collaborate with Physical Design teams for robust power delivery.
• Perform chip-package co-simulation to validate power distribution across die, package, and board.
• Review EMIR reports, debug issues, and provide closure recommendations.
• Own and automate EMIR flows using Python/Perl/TCL scripting.
• Collaborate with RTL, PD, Verification, and Packaging teams for design convergence.
• Mentor junior engineers in EMIR methodologies and best practices.

Kenntnisse

Power integrity

IR drop

Electromigration

EMIR sign-off

PDN planning

Chip-package co-design

Team leadership

Scripting (Python/Perl/TCL)

Tools

Redhawk

Voltus

Totem

Jobbeschreibung

We are seeking a EMIR Engineer to drive power integrity, IR drop, and electromigration analysis for advanced SoC designs. The ideal candidate will have strong expertise in EMIR sign-off methodology, PDN planning, and chip-package co-design, along with the ability to lead and mentor a team of engineers.

Experience :- 3 Years to 6 Years

Key Responsibilities:

• Lead IR drop, electromigration, and power integrity analysis across multiple blocks and full-chip designs.
• Define, implement, and optimize EMIR sign-off flows using industry-standard tools (Redhawk, Voltus, Totem, etc.).
• Drive PDN architecture planning and collaborate with Physical Design teams to ensure robust power delivery.
• Perform chip-package co-simulation to validate power distribution across die, package, and board.
• Review and analyze EMIR reports, debug issues, and provide recommendations to closure.
• Own and automate EMIR flows using Python/Perl/TCL scripting.
• Collaborate with cross-functional teams (RTL, PD, Verification, Packaging) for design convergence.
• Mentor and guide junior engineers in EMIR methodologies and best practices.