EMIR Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an EMIR Lead Engineer to spearhead power integrity, IR drop, and electromigration analysis for advanced SoC designs. The ideal candidate should possess 3 to 10 years of experience, with strong expertise in EMIR sign-off methodology, PDN planning, and chip-package co-design, along with skills in Python/Perl/TCL scripting. The role includes leading analysis across multiple blocks, optimizing sign-off flows, and mentoring junior engineers in best practices.

Qualifications

• 3 to 10 years of experience in EMIR lead engineering.
• Strong expertise in leading teams and mentoring junior engineers.

Responsibilities

• Lead IR drop, electromigration, and power integrity analysis.
• Define and optimize EMIR sign-off flows using industry-standard tools.
• Drive PDN architecture planning and collaborate with Physical Design teams.
• Perform chip-package co-simulation to validate power distribution.
• Review and analyze EMIR reports and provide recommendations.
• Automate EMIR flows using Python/Perl/TCL scripting.
• Collaborate with cross-functional teams for design convergence.
• Mentor junior engineers in EMIR methodologies.

Skills

EMIR sign-off methodology

PDN planning

chip-package co-design

Python scripting

Perl scripting

TCL scripting

IR drop analysis

electromigration analysis

power integrity analysis

Tools

Redhawk

Voltus

Totem

Job description

We are seeking a EMIR Lead Engineer to drive power integrity, IR drop, and electromigration analysis for advanced SoC designs. The ideal candidate will have strong expertise in EMIR sign-off methodology, PDN planning, and chip-package co-design, along with the ability to lead and mentor a team of engineers.

Experience :- 3 Years to 10 Years

Key Responsibilities:

• Lead IR drop, electromigration, and power integrity analysis across multiple blocks and full-chip designs.
• Define, implement, and optimize EMIR sign-off flows using industry-standard tools (Redhawk, Voltus, Totem, etc.).
• Drive PDN architecture planning and collaborate with Physical Design teams to ensure robust power delivery.
• Perform chip-package co-simulation to validate power distribution across die, package, and board.
• Review and analyze EMIR reports, debug issues, and provide recommendations to closure.
• Own and automate EMIR flows using Python/Perl/TCL scripting.
• Collaborate with cross-functional teams (RTL, PD, Verification, Packaging) for design convergence.
• Mentor and guide junior engineers in EMIR methodologies and best practices.