SOC / ASIC Architect

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 6,000,000 - 8,500,000; Full time

Job summary

SmartSoC - A Virtusa Company in Bengaluru, India invites an experienced RTL Micro-Architect (15+ years) to drive next-generation SoC architecture from concept to silicon.

You will define micro-architecture, translate requirements into scalable RTL designs, create architecture documents and interface specs, and collaborate with SoC, DV, DFT, PD, FPGA and firmware teams to deliver high-quality RTL, UPF and timing constraints.

Qualifications

• Extensive hands-on RTL design and SoC architecture experience.
• Proven ability to translate requirements into scalable RTL designs.
• Strong knowledge of Verilog/VHDL and design flows.

Responsibilities

• Define SoC micro-architecture and translate requirements into scalable designs.
• Develop architecture documents, block diagrams, and interface specifications.
• Drive clock, reset, power management, security, boot, and IP planning.
• Perform PPA analysis and design feasibility studies.
• Create MAS/PRD documents and drive architecture reviews to sign-off.
• Deliver high-quality RTL, UPF, and timing constraints.
• Collaborate with SoC, DV, DFT, PD, FPGA, and Firmware teams through implementation and sign-off.

Skills

Verilog/VHDL

RTL Design

SoC Micro-Architecture

High-Speed SerDes

Clock/Reset/Power Mgmt

UPF & Timing constraints

Synthesis flow

Version control

Scripting

Education

BE/B.Tech/M.Tech in ECE/EE/CS

Job description

We're Hiring | RTL #MicroArchitect Leadership/Architect | SmartSoC - A Virtusa Company

Are you passionate about architecting next-generation SoCs? We're looking for an experienced RTL Micro-Architect to join our growing semiconductor team and drive complex SoC development from architecture to silicon.

Position: #RTL Micro-Architect

Experience: 15+ Years

Company: SmartSoC - A Virtusa Company

Key Responsibilities:

• Define SoC micro-architecture and translate product requirements into scalable designs


• Develop architecture documents, block diagrams, and interface specifications


• Drive clock, reset, power management, security, boot, and IP planning


• Perform PPA (Power, Performance & Area) analysis and design feasibility studies


• Create MAS/PRD documents and drive architecture reviews to sign-off


• Deliver high-quality RTL, UPF, and timing constraints


• Collaborate with SoC, DV, DFT, PD, FPGA, and Firmware teams through implementation and sign-off

Required Skills:

• Strong expertise in Verilog/VHDL and RTL Design


• Hands-on experience in SoC Micro-Architecture and complex SoC development


• Knowledge of High-Speed SerDes and bus protocols


• Clock, Reset, and Power Management expertise


• RTL development, UPF, timing constraints, linting, and synthesis flow


• Experience working with version control systems and scripting

Qualification: BE/B.Tech/M.Tech in ECE/EE/CS or related field