RTL Design Engineer

HCLTech; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Competitive salary and benefits package

Opportunity to work on cutting-edge technologies

Potential for professional growth and development

Job summary

HCLTech is seeking a talented and experienced RTL Design Engineer in Bengaluru, India to contribute to the design and development of next-generation ASICs/SoCs. This role involves responsibilities such as developing RTL code, performing verification, and collaborating closely with design teams.

The ideal candidate will have a Bachelor's degree in Electrical Engineering or a related field with 5-7 years of experience, particularly in RTL design. Join HCLTech to work on cutting-edge technologies in a collaborative environment.

Qualifications

• 5-7 years of experience in RTL design for ASICs/SoCs.
• Proven experience in designing and verifying complex digital circuits.
• Strong understanding of digital design concepts (combinational logic, sequential logic, state machines).

Responsibilities

• Develop RTL code for complex digital circuits using HDLs.
• Perform functional verification using simulation and formal methods.
• Collaborate with design, verification, and synthesis teams.

Skills

Verilog or VHDL

Functional verification

Digital design concepts

Scripting languages (Python, Perl)

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree (a plus)

Tools

HDLs

Verification methodologies (e.g., UVM)

SDC format

Job description

We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of next-generation ASICs/SoCs. You will be responsible for all aspects of RTL design, from concept to RTL coding, verification, and integration.

Responsibilities

• Develop RTL code for complex digital circuits using Hardware Description Languages (HDLs) such as Verilog or VHDL
• Perform functional verification using simulation and formal methods
• Participate in code reviews and ensure adherence to coding standards
• Analyze timing performance and perform static timing analysis (STA)
• Collaborate with design, verification, and synthesis teams to ensure successful tape‑out
• Stay up-to-date with the latest RTL design methodologies and tools

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
• 5-7 years of experience in RTL design for ASICs/SoCs
• Proven experience in designing and verifying complex digital circuits
• Proficiency in Verilog or VHDL
• Experience with verification methodologies (e.g., UVM)
• Strong understanding of digital design concepts (combinational logic, sequential logic, state machines)
• Experience with SDC (Standard Delay Constraint) format for timing closure
• Experience with scripting languages (e.g., Python, Perl) is a plus
• Excellent communication, teamwork, and problem-solving skills
• Competitive salary and benefits package
• Opportunity to work on cutting‑edge technologies
• Collaborative and fast‑paced work environment
• Potential for professional growth and development