Senior Design Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

SmartSoC, a Virtusa Company, seeks an experienced RTL Microarchitecture Lead to drive architecture and design of next-generation SoCs in Bengaluru. Immediate availability or notice candidates preferred.

Key responsibilities include driving microarchitecture from spec to sign-off, authoring MAS/PRD documents, and delivering RTL, UPF and timing constraints with multiple teams to ensure high-performance, power-efficient silicon.

Qualifications

• Strong expertise in RTL Design & Microarchitecture.
• Proficient in Verilog or VHDL.
• Experience with RTL development, linting, UPF and timing constraints.
• Expertise in SoC integration and PPA optimization.
• Exposure to Verification, DFT and Physical Design flows.
• Proficient with Git/Perforce version control.
• Scripting skills: TCL, Python, Perl or Shell.
• Experience collaborating with Firmware teams.

Responsibilities

• Drive SoC microarchitecture from specification to sign-off.
• Develop and review microarchitecture documents including IP planning and interfaces.
• Deliver RTL, UPF and timing constraints with design teams.
• Collaborate with SoC, FPGA, DV, DFT and Physical Design teams through tape-out.
• Lead architecture reviews and sign-off for IP.
• Support design feasibility and PPA analysis.

Skills

RTL Design & Microarchitecture

Verilog/VHDL

RTL Development

UPF & Timing Constraints

SoC Integration & PPA Optimization

Verification, DFT & Physical Design

Git/Perforce

Scripting: TCL/Python/Perl/Shell

Firmware collaboration

Education

B.E./B.Tech./M.E./M.Tech. in Electronics/EE/CS

Job description

SmartSoC, a Virtusa Company, is a leading semiconductor engineering services organization specializing in end-to-end ASIC, SoC, FPGA, Embedded Systems, and VLSI design solutions. Backed by Virtusa's global engineering capabilities, SmartSoC partners with leading semiconductor companies to deliver innovative, high-quality silicon solutions across the entire chip development lifecycle.

We're looking for an experienced RTL Microarchitecture Lead to join our semiconductor team and drive the architecture and design of next-generation SoCs.

Availability: Immediate or currently serving notice candidates is preferred.

Key Responsibilities

• Drive SoC microarchitecture from specification to sign-off.
• Develop and review microarchitecture documents, including:
• SoC Fabrics & Protocol Bridges
• Fuse, Boot & Security Architecture
• IP Planning & Interfaces
• Pinout & Ball Mapping
• System & Test Planning
• Design Feasibility & PPA Analysis
• Develop microarchitecture to meet SoC performance, power, and area (PPA) targets.
• Author MAS/PRD documents and lead architecture reviews for IP sign-off.
• Deliver RTL, UPF, and timing constraints in collaboration with design teams.
• Work closely with SoC, FPGA, DV, DFT, and Physical Design teams through implementation and tape-out.
• Review implementation plans and ensure design quality through final sign-off.

Required Skills

• Strong expertise in RTL Design & Microarchitecture
• Verilog / VHDL
• RTL Development, Lint, UPF & Timing Constraints
• SoC Integration & PPA Optimization
• Experience with Verification, DFT & Physical Design flows
• Version Control Systems (Git/Perforce)
• Scripting (TCL, Python, Perl or Shell)
• Experience collaborating with Firmware teams

Preferred Profile

• Proven experience in architecting and delivering complex SoCs from concept to production.
• Strong understanding of RTL implementation, design sign-off, and semiconductor development lifecycle.
• Ability to drive cross-functional teams and technical reviews.

Qualification: B.E./B.Tech./M.E./M.Tech. in Electronics, Electrical Engineering, Computer Science, or a related field.