Rtl Design Engineer

Sasken Silicon Technolgies; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Sasken Silicon Technologies in Bengaluru, India, is seeking an experienced RTL Design Engineer to join the SoC Integration team. The role emphasizes RTL design, verification-adjacent sign-off checks, and full-chip integration flows from RTL to sign-off.

You will own RTL integration for SoC blocks, perform CDC analysis, develop SDC constraints, work with UPF power intent, run gate-level simulations, and collaborate with DV, DFT, PD teams to ensure tape-out readiness.

Qualifications

• B.Tech/B.E./M.Tech/M.E in Electronics, Electrical, VLSI, or related field.

Responsibilities

• Own and drive RTL design and integration for SoC-level blocks and top-level chip integration.
• Perform CDC analysis, identify and resolve CDC violations, and ensure robust synchronization across clock domains.
• Run and close RTL Lint checks, adhering to coding guidelines and design best practices.
• Develop, review, and maintain SDC constraints for timing closure across the design.
• Work with UPF to define power intent, including power domains and level shifters.
• Understand and implement chip-level power structures (power gating, multi-voltage domains, always-on logic).
• Perform Gate Level Simulations to validate functional correctness post-synthesis and timing-aware simulations.
• Drive end-to-end SoC design flow: RTL integration, connectivity checks, floorplan awareness, coordination with DFT, PD, and verification teams.
• Debug and resolve integration issues from block-level to top-level SoC assembly.
• Collaborate cross-functionally with architecture, verification, DFT, and physical design teams to ensure tape-out readiness.
• Document design decisions and closure reports for CDC, Lint, SDC, and UPF sign-off.

Skills

RTL design

CDC analysis

RTL Lint

SDC constraints

UPF low-power

power architecture

Gate Level Simulations

SoC design flow

cross-functional

Education

B.Tech/B.E./M.Tech/M.E ( Electronics, Electrical, VLSI)

Tools

Spyglass CDC

Questa CDC

Spyglass Lint

Ascent Lint

Job description

RTL Design Engineer

Experience Level: 811 Years
Qualification: B.Tech / B.E / M.Tech / M.E (Electronics, Electrical, VLSI, or related field)

About the Role

We are looking for an experienced RTL Engineer to join our SoC Integration team. The ideal candidate will have strong hands‑on expertise in RTL design, verification‑adjacent sign‑off checks, and full‑chip integration flows, and will play a key role in taking SoC designs from RTL through to physical‑design‑ready sign‑off.

Roles & Responsibilities

• Own and drive RTL design and integration for SoC-level blocks and top-level chip integration
• Perform Clock Domain Crossing (CDC) analysis, identify and resolve CDC violations, and ensure robust synchronization schemes across clock domains
• Run and close RTL Lint checks, ensuring adherence to coding guidelines and design best practices
• Develop, review, and maintain SDC (Synopsys Design Constraints) for timing closure across the design
• Work with UPF (Unified Power Format) to define and validate power intent, including power domains, isolation, retention, and level shifters
• Understand and implement chip-level power structures (power gating, multi‑voltage domains, always‑on logic, etc.)
• Perform Gate Level Simulations (GLS) to validate functional correctness post‑synthesis, including timing‑aware simulations
• Drive end‑to‑end SoC design flow: RTL integration, connectivity checks, floorplan awareness, and coordination with DFT, PD, and verification teams
• Debug and resolve integration issues arising from block‑level to top‑level SoC assembly
• Collaborate cross‑functionally with architecture, verification, DFT, and physical design teams to ensure smooth tape‑out readiness
• Document design decisions, methodologies, and closure reports for CDC, Lint, SDC, and UPF sign‑off

Required Skills

• Strong RTL design and coding skills (Verilog/SystemVerilog)
• Hands‑on experience with CDC analysis and closure (tools such as Spyglass CDC, Questa CDC, etc.)
• Proficiency in RTL Lint checking and resolving lint violations (Spyglass Lint, Ascent Lint, etc.)
• Strong understanding of SDC constraints — clock definitions, exceptions, false paths, multicycle paths
• Working knowledge of UPF and low‑power design methodology
• Understanding of chip‑level power architecture and power intent verification
• Experience running and debugging Gate Level Simulations (GLS)
• Solid grasp of the overall SoC design and integration flow, from RTL to sign‑off handoff
• Strong debugging skills and ability to work with cross‑functional teams (DV, DFT, PD)

Good to Have

• Exposure to any Low‑Speed or High‑Speed protocol (e.g., I2C, SPI, UART, USB, PCIe, DDR, MIPI, Ethernet)
• Scripting skills (Perl/Python/TCL) for flow automation
• Experience with formal verification tools

Soft Skills

• Strong analytical and problem‑solving ability
• Good communication skills for cross‑team coordination
• Ownership mindset with ability to work independently on complex integration tasks